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7e00a84d11
Add new compute_mqd and mes_mqd structure. V2: Rename to v12_1_compute_mqd and v12_1_mes_mqd.. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3244 lines
165 KiB
C
3244 lines
165 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef V12_STRUCTS_H_
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#define V12_STRUCTS_H_
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struct v12_gfx_mqd {
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uint32_t shadow_base_lo; // offset: 0 (0x0)
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uint32_t shadow_base_hi; // offset: 1 (0x1)
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uint32_t reserved_2; // offset: 2 (0x2)
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uint32_t reserved_3; // offset: 3 (0x3)
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uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
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uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
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uint32_t shadow_initialized; // offset: 6 (0x6)
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uint32_t ib_vmid; // offset: 7 (0x7)
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uint32_t reserved_8; // offset: 8 (0x8)
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uint32_t reserved_9; // offset: 9 (0x9)
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uint32_t reserved_10; // offset: 10 (0xA)
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uint32_t reserved_11; // offset: 11 (0xB)
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uint32_t reserved_12; // offset: 12 (0xC)
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uint32_t reserved_13; // offset: 13 (0xD)
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uint32_t reserved_14; // offset: 14 (0xE)
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uint32_t reserved_15; // offset: 15 (0xF)
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uint32_t reserved_16; // offset: 16 (0x10)
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uint32_t reserved_17; // offset: 17 (0x11)
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uint32_t reserved_18; // offset: 18 (0x12)
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uint32_t reserved_19; // offset: 19 (0x13)
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uint32_t reserved_20; // offset: 20 (0x14)
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uint32_t reserved_21; // offset: 21 (0x15)
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uint32_t reserved_22; // offset: 22 (0x16)
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uint32_t reserved_23; // offset: 23 (0x17)
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uint32_t reserved_24; // offset: 24 (0x18)
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uint32_t reserved_25; // offset: 25 (0x19)
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uint32_t reserved_26; // offset: 26 (0x1A)
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uint32_t reserved_27; // offset: 27 (0x1B)
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uint32_t reserved_28; // offset: 28 (0x1C)
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uint32_t reserved_29; // offset: 29 (0x1D)
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uint32_t reserved_30; // offset: 30 (0x1E)
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uint32_t reserved_31; // offset: 31 (0x1F)
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uint32_t reserved_32; // offset: 32 (0x20)
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uint32_t reserved_33; // offset: 33 (0x21)
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uint32_t reserved_34; // offset: 34 (0x22)
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uint32_t reserved_35; // offset: 35 (0x23)
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uint32_t reserved_36; // offset: 36 (0x24)
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uint32_t reserved_37; // offset: 37 (0x25)
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uint32_t reserved_38; // offset: 38 (0x26)
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uint32_t reserved_39; // offset: 39 (0x27)
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uint32_t reserved_40; // offset: 40 (0x28)
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uint32_t reserved_41; // offset: 41 (0x29)
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uint32_t reserved_42; // offset: 42 (0x2A)
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uint32_t reserved_43; // offset: 43 (0x2B)
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uint32_t reserved_44; // offset: 44 (0x2C)
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uint32_t reserved_45; // offset: 45 (0x2D)
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uint32_t reserved_46; // offset: 46 (0x2E)
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uint32_t reserved_47; // offset: 47 (0x2F)
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uint32_t reserved_48; // offset: 48 (0x30)
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uint32_t reserved_49; // offset: 49 (0x31)
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uint32_t reserved_50; // offset: 50 (0x32)
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uint32_t reserved_51; // offset: 51 (0x33)
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uint32_t reserved_52; // offset: 52 (0x34)
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uint32_t reserved_53; // offset: 53 (0x35)
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uint32_t reserved_54; // offset: 54 (0x36)
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uint32_t reserved_55; // offset: 55 (0x37)
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uint32_t reserved_56; // offset: 56 (0x38)
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uint32_t reserved_57; // offset: 57 (0x39)
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uint32_t reserved_58; // offset: 58 (0x3A)
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uint32_t reserved_59; // offset: 59 (0x3B)
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uint32_t reserved_60; // offset: 60 (0x3C)
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uint32_t reserved_61; // offset: 61 (0x3D)
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uint32_t reserved_62; // offset: 62 (0x3E)
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uint32_t reserved_63; // offset: 63 (0x3F)
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uint32_t reserved_64; // offset: 64 (0x40)
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uint32_t reserved_65; // offset: 65 (0x41)
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uint32_t reserved_66; // offset: 66 (0x42)
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uint32_t reserved_67; // offset: 67 (0x43)
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uint32_t reserved_68; // offset: 68 (0x44)
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uint32_t reserved_69; // offset: 69 (0x45)
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uint32_t reserved_70; // offset: 70 (0x46)
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uint32_t reserved_71; // offset: 71 (0x47)
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uint32_t reserved_72; // offset: 72 (0x48)
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uint32_t reserved_73; // offset: 73 (0x49)
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uint32_t reserved_74; // offset: 74 (0x4A)
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uint32_t reserved_75; // offset: 75 (0x4B)
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uint32_t reserved_76; // offset: 76 (0x4C)
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uint32_t reserved_77; // offset: 77 (0x4D)
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uint32_t reserved_78; // offset: 78 (0x4E)
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uint32_t reserved_79; // offset: 79 (0x4F)
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uint32_t reserved_80; // offset: 80 (0x50)
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uint32_t reserved_81; // offset: 81 (0x51)
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uint32_t reserved_82; // offset: 82 (0x52)
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uint32_t reserved_83; // offset: 83 (0x53)
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uint32_t checksum_lo; // offset: 84 (0x54)
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uint32_t checksum_hi; // offset: 85 (0x55)
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uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)
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uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)
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uint32_t reserved_88; // offset: 88 (0x58)
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uint32_t reserved_89; // offset: 89 (0x59)
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uint32_t reserved_90; // offset: 90 (0x5A)
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uint32_t reserved_91; // offset: 91 (0x5B)
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uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C)
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uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D)
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uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E)
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uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F)
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uint32_t reserved_96; // offset: 96 (0x60)
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uint32_t reserved_97; // offset: 97 (0x61)
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uint32_t reserved_98; // offset: 98 (0x62)
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uint32_t reserved_99; // offset: 99 (0x63)
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uint32_t reserved_100; // offset: 100 (0x64)
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uint32_t reserved_101; // offset: 101 (0x65)
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uint32_t reserved_102; // offset: 102 (0x66)
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uint32_t reserved_103; // offset: 103 (0x67)
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uint32_t task_shader_control_buf_addr_lo; // offset: 104 (0x68)
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uint32_t task_shader_control_buf_addr_hi; // offset: 105 (0x69)
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uint32_t task_shader_read_rptr_lo; // offset: 106 (0x6A)
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uint32_t task_shader_read_rptr_hi; // offset: 107 (0x6B)
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uint32_t task_shader_num_entries; // offset: 108 (0x6C)
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uint32_t task_shader_num_entries_bits; // offset: 109 (0x6D)
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uint32_t task_shader_ring_buffer_addr_lo; // offset: 110 (0x6E)
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uint32_t task_shader_ring_buffer_addr_hi; // offset: 111 (0x6F)
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uint32_t reserved_112; // offset: 112 (0x70)
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uint32_t reserved_113; // offset: 113 (0x71)
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uint32_t reserved_114; // offset: 114 (0x72)
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uint32_t reserved_115; // offset: 115 (0x73)
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uint32_t reserved_116; // offset: 116 (0x74)
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uint32_t reserved_117; // offset: 117 (0x75)
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uint32_t reserved_118; // offset: 118 (0x76)
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uint32_t reserved_119; // offset: 119 (0x77)
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uint32_t reserved_120; // offset: 120 (0x78)
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uint32_t reserved_121; // offset: 121 (0x79)
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uint32_t reserved_122; // offset: 122 (0x7A)
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uint32_t reserved_123; // offset: 123 (0x7B)
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uint32_t reserved_124; // offset: 124 (0x7C)
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uint32_t reserved_125; // offset: 125 (0x7D)
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uint32_t reserved_126; // offset: 126 (0x7E)
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uint32_t reserved_127; // offset: 127 (0x7F)
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uint32_t cp_mqd_base_addr; // offset: 128 (0x80)
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uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)
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uint32_t cp_gfx_hqd_active; // offset: 130 (0x82)
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uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83)
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uint32_t reserved_132; // offset: 132 (0x84)
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uint32_t reserved_133; // offset: 133 (0x85)
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uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86)
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uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87)
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uint32_t cp_gfx_hqd_base; // offset: 136 (0x88)
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uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89)
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uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A)
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uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B)
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uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C)
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uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D)
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uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E)
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uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F)
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uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90)
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uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91)
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uint32_t reserved_146; // offset: 146 (0x92)
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uint32_t reserved_147; // offset: 147 (0x93)
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uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94)
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uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95)
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uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96)
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uint32_t reserved_151; // offset: 151 (0x97)
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uint32_t reserved_152; // offset: 152 (0x98)
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uint32_t reserved_153; // offset: 153 (0x99)
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uint32_t reserved_154; // offset: 154 (0x9A)
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uint32_t reserved_155; // offset: 155 (0x9B)
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uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C)
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uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D)
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uint32_t reserved_158; // offset: 158 (0x9E)
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uint32_t reserved_159; // offset: 159 (0x9F)
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uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0)
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uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1)
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uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2)
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uint32_t reserved_163; // offset: 163 (0xA3)
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uint32_t reserved_164; // offset: 164 (0xA4)
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uint32_t reserved_165; // offset: 165 (0xA5)
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uint32_t reserved_166; // offset: 166 (0xA6)
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uint32_t reserved_167; // offset: 167 (0xA7)
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uint32_t reserved_168; // offset: 168 (0xA8)
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uint32_t reserved_169; // offset: 169 (0xA9)
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uint32_t reserved_170; // offset: 170 (0xAA)
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uint32_t reserved_171; // offset: 171 (0xAB)
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uint32_t reserved_172; // offset: 172 (0xAC)
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uint32_t reserved_173; // offset: 173 (0xAD)
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uint32_t reserved_174; // offset: 174 (0xAE)
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uint32_t reserved_175; // offset: 175 (0xAF)
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uint32_t reserved_176; // offset: 176 (0xB0)
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uint32_t reserved_177; // offset: 177 (0xB1)
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uint32_t reserved_178; // offset: 178 (0xB2)
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uint32_t reserved_179; // offset: 179 (0xB3)
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uint32_t reserved_180; // offset: 180 (0xB4)
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uint32_t reserved_181; // offset: 181 (0xB5)
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uint32_t reserved_182; // offset: 182 (0xB6)
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uint32_t reserved_183; // offset: 183 (0xB7)
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uint32_t reserved_184; // offset: 184 (0xB8)
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uint32_t reserved_185; // offset: 185 (0xB9)
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uint32_t reserved_186; // offset: 186 (0xBA)
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uint32_t reserved_187; // offset: 187 (0xBB)
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uint32_t reserved_188; // offset: 188 (0xBC)
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uint32_t reserved_189; // offset: 189 (0xBD)
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uint32_t reserved_190; // offset: 190 (0xBE)
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uint32_t reserved_191; // offset: 191 (0xBF)
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uint32_t reserved_192; // offset: 192 (0xC0)
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uint32_t reserved_193; // offset: 193 (0xC1)
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uint32_t reserved_194; // offset: 194 (0xC2)
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uint32_t reserved_195; // offset: 195 (0xC3)
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uint32_t reserved_196; // offset: 196 (0xC4)
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uint32_t reserved_197; // offset: 197 (0xC5)
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uint32_t reserved_198; // offset: 198 (0xC6)
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uint32_t reserved_199; // offset: 199 (0xC7)
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uint32_t reserved_200; // offset: 200 (0xC8)
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uint32_t reserved_201; // offset: 201 (0xC9)
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uint32_t reserved_202; // offset: 202 (0xCA)
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uint32_t reserved_203; // offset: 203 (0xCB)
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uint32_t reserved_204; // offset: 204 (0xCC)
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uint32_t reserved_205; // offset: 205 (0xCD)
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uint32_t reserved_206; // offset: 206 (0xCE)
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uint32_t reserved_207; // offset: 207 (0xCF)
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uint32_t reserved_208; // offset: 208 (0xD0)
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uint32_t reserved_209; // offset: 209 (0xD1)
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uint32_t reserved_210; // offset: 210 (0xD2)
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uint32_t reserved_211; // offset: 211 (0xD3)
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uint32_t reserved_212; // offset: 212 (0xD4)
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uint32_t reserved_213; // offset: 213 (0xD5)
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uint32_t reserved_214; // offset: 214 (0xD6)
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uint32_t reserved_215; // offset: 215 (0xD7)
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uint32_t reserved_216; // offset: 216 (0xD8)
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uint32_t reserved_217; // offset: 217 (0xD9)
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uint32_t reserved_218; // offset: 218 (0xDA)
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uint32_t reserved_219; // offset: 219 (0xDB)
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uint32_t reserved_220; // offset: 220 (0xDC)
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uint32_t reserved_221; // offset: 221 (0xDD)
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uint32_t reserved_222; // offset: 222 (0xDE)
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uint32_t reserved_223; // offset: 223 (0xDF)
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uint32_t reserved_224; // offset: 224 (0xE0)
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uint32_t reserved_225; // offset: 225 (0xE1)
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uint32_t reserved_226; // offset: 226 (0xE2)
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uint32_t reserved_227; // offset: 227 (0xE3)
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uint32_t reserved_228; // offset: 228 (0xE4)
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uint32_t reserved_229; // offset: 229 (0xE5)
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uint32_t reserved_230; // offset: 230 (0xE6)
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uint32_t reserved_231; // offset: 231 (0xE7)
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uint32_t reserved_232; // offset: 232 (0xE8)
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uint32_t reserved_233; // offset: 233 (0xE9)
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uint32_t reserved_234; // offset: 234 (0xEA)
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uint32_t reserved_235; // offset: 235 (0xEB)
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uint32_t reserved_236; // offset: 236 (0xEC)
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uint32_t reserved_237; // offset: 237 (0xED)
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uint32_t reserved_238; // offset: 238 (0xEE)
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uint32_t reserved_239; // offset: 239 (0xEF)
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uint32_t reserved_240; // offset: 240 (0xF0)
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uint32_t reserved_241; // offset: 241 (0xF1)
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uint32_t reserved_242; // offset: 242 (0xF2)
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uint32_t reserved_243; // offset: 243 (0xF3)
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uint32_t reserved_244; // offset: 244 (0xF4)
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uint32_t reserved_245; // offset: 245 (0xF5)
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uint32_t reserved_246; // offset: 246 (0xF6)
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uint32_t reserved_247; // offset: 247 (0xF7)
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uint32_t reserved_248; // offset: 248 (0xF8)
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uint32_t reserved_249; // offset: 249 (0xF9)
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uint32_t reserved_250; // offset: 250 (0xFA)
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uint32_t reserved_251; // offset: 251 (0xFB)
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uint32_t reserved_252; // offset: 252 (0xFC)
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uint32_t reserved_253; // offset: 253 (0xFD)
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uint32_t reserved_254; // offset: 254 (0xFE)
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uint32_t reserved_255; // offset: 255 (0xFF)
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uint32_t reserved_256; // offset: 256 (0x100)
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uint32_t reserved_257; // offset: 257 (0x101)
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uint32_t reserved_258; // offset: 258 (0x102)
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uint32_t reserved_259; // offset: 259 (0x103)
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uint32_t reserved_260; // offset: 260 (0x104)
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uint32_t reserved_261; // offset: 261 (0x105)
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uint32_t reserved_262; // offset: 262 (0x106)
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uint32_t reserved_263; // offset: 263 (0x107)
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uint32_t reserved_264; // offset: 264 (0x108)
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uint32_t reserved_265; // offset: 265 (0x109)
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uint32_t reserved_266; // offset: 266 (0x10A)
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uint32_t reserved_267; // offset: 267 (0x10B)
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uint32_t reserved_268; // offset: 268 (0x10C)
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uint32_t reserved_269; // offset: 269 (0x10D)
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uint32_t reserved_270; // offset: 270 (0x10E)
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uint32_t reserved_271; // offset: 271 (0x10F)
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uint32_t dfwx_flags; // offset: 272 (0x110)
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uint32_t dfwx_slot; // offset: 273 (0x111)
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uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112)
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uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113)
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uint32_t reserved_276; // offset: 276 (0x114)
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uint32_t reserved_277; // offset: 277 (0x115)
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uint32_t reserved_278; // offset: 278 (0x116)
|
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uint32_t reserved_279; // offset: 279 (0x117)
|
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uint32_t reserved_280; // offset: 280 (0x118)
|
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uint32_t reserved_281; // offset: 281 (0x119)
|
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uint32_t reserved_282; // offset: 282 (0x11A)
|
|
uint32_t reserved_283; // offset: 283 (0x11B)
|
|
uint32_t reserved_284; // offset: 284 (0x11C)
|
|
uint32_t reserved_285; // offset: 285 (0x11D)
|
|
uint32_t reserved_286; // offset: 286 (0x11E)
|
|
uint32_t reserved_287; // offset: 287 (0x11F)
|
|
uint32_t reserved_288; // offset: 288 (0x120)
|
|
uint32_t reserved_289; // offset: 289 (0x121)
|
|
uint32_t reserved_290; // offset: 290 (0x122)
|
|
uint32_t reserved_291; // offset: 291 (0x123)
|
|
uint32_t reserved_292; // offset: 292 (0x124)
|
|
uint32_t reserved_293; // offset: 293 (0x125)
|
|
uint32_t reserved_294; // offset: 294 (0x126)
|
|
uint32_t reserved_295; // offset: 295 (0x127)
|
|
uint32_t reserved_296; // offset: 296 (0x128)
|
|
uint32_t reserved_297; // offset: 297 (0x129)
|
|
uint32_t reserved_298; // offset: 298 (0x12A)
|
|
uint32_t reserved_299; // offset: 299 (0x12B)
|
|
uint32_t reserved_300; // offset: 300 (0x12C)
|
|
uint32_t reserved_301; // offset: 301 (0x12D)
|
|
uint32_t reserved_302; // offset: 302 (0x12E)
|
|
uint32_t reserved_303; // offset: 303 (0x12F)
|
|
uint32_t reserved_304; // offset: 304 (0x130)
|
|
uint32_t reserved_305; // offset: 305 (0x131)
|
|
uint32_t reserved_306; // offset: 306 (0x132)
|
|
uint32_t reserved_307; // offset: 307 (0x133)
|
|
uint32_t reserved_308; // offset: 308 (0x134)
|
|
uint32_t reserved_309; // offset: 309 (0x135)
|
|
uint32_t reserved_310; // offset: 310 (0x136)
|
|
uint32_t reserved_311; // offset: 311 (0x137)
|
|
uint32_t reserved_312; // offset: 312 (0x138)
|
|
uint32_t reserved_313; // offset: 313 (0x139)
|
|
uint32_t reserved_314; // offset: 314 (0x13A)
|
|
uint32_t reserved_315; // offset: 315 (0x13B)
|
|
uint32_t reserved_316; // offset: 316 (0x13C)
|
|
uint32_t reserved_317; // offset: 317 (0x13D)
|
|
uint32_t reserved_318; // offset: 318 (0x13E)
|
|
uint32_t reserved_319; // offset: 319 (0x13F)
|
|
uint32_t reserved_320; // offset: 320 (0x140)
|
|
uint32_t reserved_321; // offset: 321 (0x141)
|
|
uint32_t reserved_322; // offset: 322 (0x142)
|
|
uint32_t reserved_323; // offset: 323 (0x143)
|
|
uint32_t reserved_324; // offset: 324 (0x144)
|
|
uint32_t reserved_325; // offset: 325 (0x145)
|
|
uint32_t reserved_326; // offset: 326 (0x146)
|
|
uint32_t reserved_327; // offset: 327 (0x147)
|
|
uint32_t reserved_328; // offset: 328 (0x148)
|
|
uint32_t reserved_329; // offset: 329 (0x149)
|
|
uint32_t reserved_330; // offset: 330 (0x14A)
|
|
uint32_t reserved_331; // offset: 331 (0x14B)
|
|
uint32_t reserved_332; // offset: 332 (0x14C)
|
|
uint32_t reserved_333; // offset: 333 (0x14D)
|
|
uint32_t reserved_334; // offset: 334 (0x14E)
|
|
uint32_t reserved_335; // offset: 335 (0x14F)
|
|
uint32_t reserved_336; // offset: 336 (0x150)
|
|
uint32_t reserved_337; // offset: 337 (0x151)
|
|
uint32_t reserved_338; // offset: 338 (0x152)
|
|
uint32_t reserved_339; // offset: 339 (0x153)
|
|
uint32_t reserved_340; // offset: 340 (0x154)
|
|
uint32_t reserved_341; // offset: 341 (0x155)
|
|
uint32_t reserved_342; // offset: 342 (0x156)
|
|
uint32_t reserved_343; // offset: 343 (0x157)
|
|
uint32_t reserved_344; // offset: 344 (0x158)
|
|
uint32_t reserved_345; // offset: 345 (0x159)
|
|
uint32_t reserved_346; // offset: 346 (0x15A)
|
|
uint32_t reserved_347; // offset: 347 (0x15B)
|
|
uint32_t reserved_348; // offset: 348 (0x15C)
|
|
uint32_t reserved_349; // offset: 349 (0x15D)
|
|
uint32_t reserved_350; // offset: 350 (0x15E)
|
|
uint32_t reserved_351; // offset: 351 (0x15F)
|
|
uint32_t reserved_352; // offset: 352 (0x160)
|
|
uint32_t reserved_353; // offset: 353 (0x161)
|
|
uint32_t reserved_354; // offset: 354 (0x162)
|
|
uint32_t reserved_355; // offset: 355 (0x163)
|
|
uint32_t reserved_356; // offset: 356 (0x164)
|
|
uint32_t reserved_357; // offset: 357 (0x165)
|
|
uint32_t reserved_358; // offset: 358 (0x166)
|
|
uint32_t reserved_359; // offset: 359 (0x167)
|
|
uint32_t reserved_360; // offset: 360 (0x168)
|
|
uint32_t reserved_361; // offset: 361 (0x169)
|
|
uint32_t reserved_362; // offset: 362 (0x16A)
|
|
uint32_t reserved_363; // offset: 363 (0x16B)
|
|
uint32_t reserved_364; // offset: 364 (0x16C)
|
|
uint32_t reserved_365; // offset: 365 (0x16D)
|
|
uint32_t reserved_366; // offset: 366 (0x16E)
|
|
uint32_t reserved_367; // offset: 367 (0x16F)
|
|
uint32_t reserved_368; // offset: 368 (0x170)
|
|
uint32_t reserved_369; // offset: 369 (0x171)
|
|
uint32_t reserved_370; // offset: 370 (0x172)
|
|
uint32_t reserved_371; // offset: 371 (0x173)
|
|
uint32_t reserved_372; // offset: 372 (0x174)
|
|
uint32_t reserved_373; // offset: 373 (0x175)
|
|
uint32_t reserved_374; // offset: 374 (0x176)
|
|
uint32_t reserved_375; // offset: 375 (0x177)
|
|
uint32_t reserved_376; // offset: 376 (0x178)
|
|
uint32_t reserved_377; // offset: 377 (0x179)
|
|
uint32_t reserved_378; // offset: 378 (0x17A)
|
|
uint32_t reserved_379; // offset: 379 (0x17B)
|
|
uint32_t reserved_380; // offset: 380 (0x17C)
|
|
uint32_t reserved_381; // offset: 381 (0x17D)
|
|
uint32_t reserved_382; // offset: 382 (0x17E)
|
|
uint32_t reserved_383; // offset: 383 (0x17F)
|
|
uint32_t reserved_384; // offset: 384 (0x180)
|
|
uint32_t reserved_385; // offset: 385 (0x181)
|
|
uint32_t reserved_386; // offset: 386 (0x182)
|
|
uint32_t reserved_387; // offset: 387 (0x183)
|
|
uint32_t reserved_388; // offset: 388 (0x184)
|
|
uint32_t reserved_389; // offset: 389 (0x185)
|
|
uint32_t reserved_390; // offset: 390 (0x186)
|
|
uint32_t reserved_391; // offset: 391 (0x187)
|
|
uint32_t reserved_392; // offset: 392 (0x188)
|
|
uint32_t reserved_393; // offset: 393 (0x189)
|
|
uint32_t reserved_394; // offset: 394 (0x18A)
|
|
uint32_t reserved_395; // offset: 395 (0x18B)
|
|
uint32_t reserved_396; // offset: 396 (0x18C)
|
|
uint32_t reserved_397; // offset: 397 (0x18D)
|
|
uint32_t reserved_398; // offset: 398 (0x18E)
|
|
uint32_t reserved_399; // offset: 399 (0x18F)
|
|
uint32_t reserved_400; // offset: 400 (0x190)
|
|
uint32_t reserved_401; // offset: 401 (0x191)
|
|
uint32_t reserved_402; // offset: 402 (0x192)
|
|
uint32_t reserved_403; // offset: 403 (0x193)
|
|
uint32_t reserved_404; // offset: 404 (0x194)
|
|
uint32_t reserved_405; // offset: 405 (0x195)
|
|
uint32_t reserved_406; // offset: 406 (0x196)
|
|
uint32_t reserved_407; // offset: 407 (0x197)
|
|
uint32_t reserved_408; // offset: 408 (0x198)
|
|
uint32_t reserved_409; // offset: 409 (0x199)
|
|
uint32_t reserved_410; // offset: 410 (0x19A)
|
|
uint32_t reserved_411; // offset: 411 (0x19B)
|
|
uint32_t reserved_412; // offset: 412 (0x19C)
|
|
uint32_t reserved_413; // offset: 413 (0x19D)
|
|
uint32_t reserved_414; // offset: 414 (0x19E)
|
|
uint32_t reserved_415; // offset: 415 (0x19F)
|
|
uint32_t reserved_416; // offset: 416 (0x1A0)
|
|
uint32_t reserved_417; // offset: 417 (0x1A1)
|
|
uint32_t reserved_418; // offset: 418 (0x1A2)
|
|
uint32_t reserved_419; // offset: 419 (0x1A3)
|
|
uint32_t reserved_420; // offset: 420 (0x1A4)
|
|
uint32_t reserved_421; // offset: 421 (0x1A5)
|
|
uint32_t reserved_422; // offset: 422 (0x1A6)
|
|
uint32_t reserved_423; // offset: 423 (0x1A7)
|
|
uint32_t reserved_424; // offset: 424 (0x1A8)
|
|
uint32_t reserved_425; // offset: 425 (0x1A9)
|
|
uint32_t reserved_426; // offset: 426 (0x1AA)
|
|
uint32_t reserved_427; // offset: 427 (0x1AB)
|
|
uint32_t reserved_428; // offset: 428 (0x1AC)
|
|
uint32_t reserved_429; // offset: 429 (0x1AD)
|
|
uint32_t reserved_430; // offset: 430 (0x1AE)
|
|
uint32_t reserved_431; // offset: 431 (0x1AF)
|
|
uint32_t reserved_432; // offset: 432 (0x1B0)
|
|
uint32_t reserved_433; // offset: 433 (0x1B1)
|
|
uint32_t reserved_434; // offset: 434 (0x1B2)
|
|
uint32_t reserved_435; // offset: 435 (0x1B3)
|
|
uint32_t reserved_436; // offset: 436 (0x1B4)
|
|
uint32_t reserved_437; // offset: 437 (0x1B5)
|
|
uint32_t reserved_438; // offset: 438 (0x1B6)
|
|
uint32_t reserved_439; // offset: 439 (0x1B7)
|
|
uint32_t reserved_440; // offset: 440 (0x1B8)
|
|
uint32_t reserved_441; // offset: 441 (0x1B9)
|
|
uint32_t reserved_442; // offset: 442 (0x1BA)
|
|
uint32_t reserved_443; // offset: 443 (0x1BB)
|
|
uint32_t reserved_444; // offset: 444 (0x1BC)
|
|
uint32_t reserved_445; // offset: 445 (0x1BD)
|
|
uint32_t reserved_446; // offset: 446 (0x1BE)
|
|
uint32_t reserved_447; // offset: 447 (0x1BF)
|
|
uint32_t reserved_448; // offset: 448 (0x1C0)
|
|
uint32_t reserved_449; // offset: 449 (0x1C1)
|
|
uint32_t reserved_450; // offset: 450 (0x1C2)
|
|
uint32_t reserved_451; // offset: 451 (0x1C3)
|
|
uint32_t reserved_452; // offset: 452 (0x1C4)
|
|
uint32_t reserved_453; // offset: 453 (0x1C5)
|
|
uint32_t reserved_454; // offset: 454 (0x1C6)
|
|
uint32_t reserved_455; // offset: 455 (0x1C7)
|
|
uint32_t reserved_456; // offset: 456 (0x1C8)
|
|
uint32_t reserved_457; // offset: 457 (0x1C9)
|
|
uint32_t reserved_458; // offset: 458 (0x1CA)
|
|
uint32_t reserved_459; // offset: 459 (0x1CB)
|
|
uint32_t reserved_460; // offset: 460 (0x1CC)
|
|
uint32_t reserved_461; // offset: 461 (0x1CD)
|
|
uint32_t reserved_462; // offset: 462 (0x1CE)
|
|
uint32_t reserved_463; // offset: 463 (0x1CF)
|
|
uint32_t reserved_464; // offset: 464 (0x1D0)
|
|
uint32_t reserved_465; // offset: 465 (0x1D1)
|
|
uint32_t reserved_466; // offset: 466 (0x1D2)
|
|
uint32_t reserved_467; // offset: 467 (0x1D3)
|
|
uint32_t reserved_468; // offset: 468 (0x1D4)
|
|
uint32_t reserved_469; // offset: 469 (0x1D5)
|
|
uint32_t reserved_470; // offset: 470 (0x1D6)
|
|
uint32_t reserved_471; // offset: 471 (0x1D7)
|
|
uint32_t reserved_472; // offset: 472 (0x1D8)
|
|
uint32_t reserved_473; // offset: 473 (0x1D9)
|
|
uint32_t reserved_474; // offset: 474 (0x1DA)
|
|
uint32_t reserved_475; // offset: 475 (0x1DB)
|
|
uint32_t reserved_476; // offset: 476 (0x1DC)
|
|
uint32_t reserved_477; // offset: 477 (0x1DD)
|
|
uint32_t reserved_478; // offset: 478 (0x1DE)
|
|
uint32_t reserved_479; // offset: 479 (0x1DF)
|
|
uint32_t reserved_480; // offset: 480 (0x1E0)
|
|
uint32_t reserved_481; // offset: 481 (0x1E1)
|
|
uint32_t reserved_482; // offset: 482 (0x1E2)
|
|
uint32_t reserved_483; // offset: 483 (0x1E3)
|
|
uint32_t reserved_484; // offset: 484 (0x1E4)
|
|
uint32_t reserved_485; // offset: 485 (0x1E5)
|
|
uint32_t reserved_486; // offset: 486 (0x1E6)
|
|
uint32_t reserved_487; // offset: 487 (0x1E7)
|
|
uint32_t reserved_488; // offset: 488 (0x1E8)
|
|
uint32_t reserved_489; // offset: 489 (0x1E9)
|
|
uint32_t reserved_490; // offset: 490 (0x1EA)
|
|
uint32_t reserved_491; // offset: 491 (0x1EB)
|
|
uint32_t reserved_492; // offset: 492 (0x1EC)
|
|
uint32_t reserved_493; // offset: 493 (0x1ED)
|
|
uint32_t reserved_494; // offset: 494 (0x1EE)
|
|
uint32_t reserved_495; // offset: 495 (0x1EF)
|
|
uint32_t reserved_496; // offset: 496 (0x1F0)
|
|
uint32_t reserved_497; // offset: 497 (0x1F1)
|
|
uint32_t reserved_498; // offset: 498 (0x1F2)
|
|
uint32_t reserved_499; // offset: 499 (0x1F3)
|
|
uint32_t reserved_500; // offset: 500 (0x1F4)
|
|
uint32_t reserved_501; // offset: 501 (0x1F5)
|
|
uint32_t reserved_502; // offset: 502 (0x1F6)
|
|
uint32_t reserved_503; // offset: 503 (0x1F7)
|
|
uint32_t reserved_504; // offset: 504 (0x1F8)
|
|
uint32_t reserved_505; // offset: 505 (0x1F9)
|
|
uint32_t reserved_506; // offset: 506 (0x1FA)
|
|
uint32_t reserved_507; // offset: 507 (0x1FB)
|
|
uint32_t reserved_508; // offset: 508 (0x1FC)
|
|
uint32_t reserved_509; // offset: 509 (0x1FD)
|
|
uint32_t fence_address_lo; // offset: 510 (0x1FE)
|
|
uint32_t fence_address_hi; // offset: 511 (0x1FF)
|
|
};
|
|
|
|
struct v12_sdma_mqd {
|
|
uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0)
|
|
uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1)
|
|
uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2)
|
|
uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3)
|
|
uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4)
|
|
uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5)
|
|
uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6)
|
|
uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 7 (0x7)
|
|
uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 8 (0x8)
|
|
uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9)
|
|
uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA)
|
|
uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB)
|
|
uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC)
|
|
uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD)
|
|
uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE)
|
|
uint32_t sdmax_rlcx_doorbell; // offset: 15 (0xF)
|
|
uint32_t sdmax_rlcx_doorbell_log; // offset: 16 (0x10)
|
|
uint32_t sdmax_rlcx_doorbell_offset; // offset: 17 (0x11)
|
|
uint32_t sdmax_rlcx_csa_addr_lo; // offset: 18 (0x12)
|
|
uint32_t sdmax_rlcx_csa_addr_hi; // offset: 19 (0x13)
|
|
uint32_t sdmax_rlcx_sched_cntl; // offset: 20 (0x14)
|
|
uint32_t sdmax_rlcx_ib_sub_remain; // offset: 21 (0x15)
|
|
uint32_t sdmax_rlcx_preempt; // offset: 22 (0x16)
|
|
uint32_t sdmax_rlcx_dummy_reg; // offset: 23 (0x17)
|
|
uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 24 (0x18)
|
|
uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 25 (0x19)
|
|
uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 26 (0x1A)
|
|
uint32_t sdmax_rlcx_minor_ptr_update; // offset: 27 (0x1B)
|
|
uint32_t sdmax_rlcx_mcu_dbg0; // offset: 28 (0x1C)
|
|
uint32_t sdmax_rlcx_mcu_dbg1; // offset: 29 (0x1D)
|
|
uint32_t sdmax_rlcx_context_switch_status; // offset: 30 (0x1E)
|
|
uint32_t sdmax_rlcx_midcmd_cntl; // offset: 31 (0x1F)
|
|
uint32_t sdmax_rlcx_midcmd_data0; // offset: 32 (0x20)
|
|
uint32_t sdmax_rlcx_midcmd_data1; // offset: 33 (0x21)
|
|
uint32_t sdmax_rlcx_midcmd_data2; // offset: 34 (0x22)
|
|
uint32_t sdmax_rlcx_midcmd_data3; // offset: 35 (0x23)
|
|
uint32_t sdmax_rlcx_midcmd_data4; // offset: 36 (0x24)
|
|
uint32_t sdmax_rlcx_midcmd_data5; // offset: 37 (0x25)
|
|
uint32_t sdmax_rlcx_midcmd_data6; // offset: 38 (0x26)
|
|
uint32_t sdmax_rlcx_midcmd_data7; // offset: 39 (0x27)
|
|
uint32_t sdmax_rlcx_midcmd_data8; // offset: 40 (0x28)
|
|
uint32_t sdmax_rlcx_midcmd_data9; // offset: 41 (0x29)
|
|
uint32_t sdmax_rlcx_midcmd_data10; // offset: 42 (0x2A)
|
|
uint32_t sdmax_rlcx_wait_unsatisfied_thd; // offset: 43 (0x2B)
|
|
uint32_t sdmax_rlcx_mqd_base_addr_lo; // offset: 44 (0x2C)
|
|
uint32_t sdmax_rlcx_mqd_base_addr_hi; // offset: 45 (0x2D)
|
|
uint32_t sdmax_rlcx_mqd_control; // offset: 46 (0x2E)
|
|
uint32_t reserved_47; // offset: 47 (0x2F)
|
|
uint32_t reserved_48; // offset: 48 (0x30)
|
|
uint32_t reserved_49; // offset: 49 (0x31)
|
|
uint32_t reserved_50; // offset: 50 (0x32)
|
|
uint32_t reserved_51; // offset: 51 (0x33)
|
|
uint32_t reserved_52; // offset: 52 (0x34)
|
|
uint32_t reserved_53; // offset: 53 (0x35)
|
|
uint32_t reserved_54; // offset: 54 (0x36)
|
|
uint32_t reserved_55; // offset: 55 (0x37)
|
|
uint32_t reserved_56; // offset: 56 (0x38)
|
|
uint32_t reserved_57; // offset: 57 (0x39)
|
|
uint32_t reserved_58; // offset: 58 (0x3A)
|
|
uint32_t reserved_59; // offset: 59 (0x3B)
|
|
uint32_t reserved_60; // offset: 60 (0x3C)
|
|
uint32_t reserved_61; // offset: 61 (0x3D)
|
|
uint32_t reserved_62; // offset: 62 (0x3E)
|
|
uint32_t reserved_63; // offset: 63 (0x3F)
|
|
uint32_t reserved_64; // offset: 64 (0x40)
|
|
uint32_t reserved_65; // offset: 65 (0x41)
|
|
uint32_t reserved_66; // offset: 66 (0x42)
|
|
uint32_t reserved_67; // offset: 67 (0x43)
|
|
uint32_t reserved_68; // offset: 68 (0x44)
|
|
uint32_t reserved_69; // offset: 69 (0x45)
|
|
uint32_t reserved_70; // offset: 70 (0x46)
|
|
uint32_t reserved_71; // offset: 0 (0x47)
|
|
uint32_t reserved_72; // offset: 1 (0x48)
|
|
uint32_t reserved_73; // offset: 2 (0x49)
|
|
uint32_t reserved_74; // offset: 3 (0x4A)
|
|
uint32_t reserved_75; // offset: 4 (0x4B)
|
|
uint32_t reserved_76; // offset: 5 (0x4C)
|
|
uint32_t reserved_77; // offset: 6 (0x4D)
|
|
uint32_t reserved_78; // offset: 7 (0x4E)
|
|
uint32_t reserved_79; // offset: 79 (0x4F)
|
|
uint32_t reserved_80; // offset: 80 (0x50)
|
|
uint32_t reserved_81; // offset: 81 (0x51)
|
|
uint32_t reserved_82; // offset: 82 (0x52)
|
|
uint32_t reserved_83; // offset: 83 (0x53)
|
|
uint32_t reserved_84; // offset: 84 (0x54)
|
|
uint32_t reserved_85; // offset: 85 (0x55)
|
|
uint32_t reserved_86; // offset: 86 (0x56)
|
|
uint32_t reserved_87; // offset: 87 (0x57)
|
|
uint32_t reserved_88; // offset: 88 (0x58)
|
|
uint32_t reserved_89; // offset: 89 (0x59)
|
|
uint32_t reserved_90; // offset: 90 (0x5A)
|
|
uint32_t reserved_91; // offset: 91 (0x5B)
|
|
uint32_t reserved_92; // offset: 92 (0x5C)
|
|
uint32_t reserved_93; // offset: 93 (0x5D)
|
|
uint32_t reserved_94; // offset: 94 (0x5E)
|
|
uint32_t reserved_95; // offset: 95 (0x5F)
|
|
uint32_t reserved_96; // offset: 96 (0x60)
|
|
uint32_t reserved_97; // offset: 97 (0x61)
|
|
uint32_t reserved_98; // offset: 98 (0x62)
|
|
uint32_t reserved_99; // offset: 99 (0x63)
|
|
uint32_t reserved_100; // offset: 100 (0x64)
|
|
uint32_t reserved_101; // offset: 101 (0x65)
|
|
uint32_t reserved_102; // offset: 102 (0x66)
|
|
uint32_t reserved_103; // offset: 103 (0x67)
|
|
uint32_t reserved_104; // offset: 104 (0x68)
|
|
uint32_t reserved_105; // offset: 105 (0x69)
|
|
uint32_t reserved_106; // offset: 106 (0x6A)
|
|
uint32_t reserved_107; // offset: 107 (0x6B)
|
|
uint32_t reserved_108; // offset: 108 (0x6C)
|
|
uint32_t reserved_109; // offset: 109 (0x6D)
|
|
uint32_t reserved_110; // offset: 110 (0x6E)
|
|
uint32_t reserved_111; // offset: 111 (0x6F)
|
|
uint32_t reserved_112; // offset: 112 (0x70)
|
|
uint32_t reserved_113; // offset: 113 (0x71)
|
|
uint32_t reserved_114; // offset: 114 (0x72)
|
|
uint32_t reserved_115; // offset: 115 (0x73)
|
|
uint32_t reserved_116; // offset: 116 (0x74)
|
|
uint32_t reserved_117; // offset: 117 (0x75)
|
|
uint32_t reserved_118; // offset: 118 (0x76)
|
|
uint32_t reserved_119; // offset: 119 (0x77)
|
|
uint32_t reserved_120; // offset: 120 (0x78)
|
|
uint32_t reserved_121; // offset: 121 (0x79)
|
|
uint32_t reserved_122; // offset: 122 (0x7A)
|
|
uint32_t reserved_123; // offset: 123 (0x7B)
|
|
uint32_t reserved_124; // offset: 124 (0x7C)
|
|
uint32_t reserved_125; // offset: 125 (0x7D)
|
|
/* reserved_126,127: repurposed for driver-internal use */
|
|
uint32_t sdma_engine_id;
|
|
uint32_t sdma_queue_id;
|
|
};
|
|
|
|
struct v12_compute_mqd {
|
|
uint32_t header; // offset: 0 (0x0)
|
|
uint32_t compute_dispatch_initiator; // offset: 1 (0x1)
|
|
uint32_t compute_dim_x; // offset: 2 (0x2)
|
|
uint32_t compute_dim_y; // offset: 3 (0x3)
|
|
uint32_t compute_dim_z; // offset: 4 (0x4)
|
|
uint32_t compute_start_x; // offset: 5 (0x5)
|
|
uint32_t compute_start_y; // offset: 6 (0x6)
|
|
uint32_t compute_start_z; // offset: 7 (0x7)
|
|
uint32_t compute_num_thread_x; // offset: 8 (0x8)
|
|
uint32_t compute_num_thread_y; // offset: 9 (0x9)
|
|
uint32_t compute_num_thread_z; // offset: 10 (0xA)
|
|
uint32_t compute_pipelinestat_enable; // offset: 11 (0xB)
|
|
uint32_t compute_perfcount_enable; // offset: 12 (0xC)
|
|
uint32_t compute_pgm_lo; // offset: 13 (0xD)
|
|
uint32_t compute_pgm_hi; // offset: 14 (0xE)
|
|
uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF)
|
|
uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10)
|
|
uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11)
|
|
uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12)
|
|
uint32_t compute_pgm_rsrc1; // offset: 19 (0x13)
|
|
uint32_t compute_pgm_rsrc2; // offset: 20 (0x14)
|
|
uint32_t compute_vmid; // offset: 21 (0x15)
|
|
uint32_t compute_resource_limits; // offset: 22 (0x16)
|
|
uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17)
|
|
uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18)
|
|
uint32_t compute_tmpring_size; // offset: 25 (0x19)
|
|
uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A)
|
|
uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B)
|
|
uint32_t compute_restart_x; // offset: 28 (0x1C)
|
|
uint32_t compute_restart_y; // offset: 29 (0x1D)
|
|
uint32_t compute_restart_z; // offset: 30 (0x1E)
|
|
uint32_t compute_thread_trace_enable; // offset: 31 (0x1F)
|
|
uint32_t compute_misc_reserved; // offset: 32 (0x20)
|
|
uint32_t compute_dispatch_id; // offset: 33 (0x21)
|
|
uint32_t compute_threadgroup_id; // offset: 34 (0x22)
|
|
uint32_t compute_req_ctrl; // offset: 35 (0x23)
|
|
uint32_t reserved_36; // offset: 36 (0x24)
|
|
uint32_t compute_user_accum_0; // offset: 37 (0x25)
|
|
uint32_t compute_user_accum_1; // offset: 38 (0x26)
|
|
uint32_t compute_user_accum_2; // offset: 39 (0x27)
|
|
uint32_t compute_user_accum_3; // offset: 40 (0x28)
|
|
uint32_t compute_pgm_rsrc3; // offset: 41 (0x29)
|
|
uint32_t compute_ddid_index; // offset: 42 (0x2A)
|
|
uint32_t compute_shader_chksum; // offset: 43 (0x2B)
|
|
uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C)
|
|
uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D)
|
|
uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E)
|
|
uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F)
|
|
uint32_t compute_dispatch_interleave; // offset: 48 (0x30)
|
|
uint32_t compute_relaunch; // offset: 49 (0x31)
|
|
uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32)
|
|
uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33)
|
|
uint32_t compute_wave_restore_control; // offset: 52 (0x34)
|
|
uint32_t reserved_53; // offset: 53 (0x35)
|
|
uint32_t reserved_54; // offset: 54 (0x36)
|
|
uint32_t reserved_55; // offset: 55 (0x37)
|
|
uint32_t reserved_56; // offset: 56 (0x38)
|
|
uint32_t reserved_57; // offset: 57 (0x39)
|
|
uint32_t reserved_58; // offset: 58 (0x3A)
|
|
uint32_t compute_static_thread_mgmt_se8; // offset: 59 (0x3B)
|
|
uint32_t reserved_60; // offset: 60 (0x3C)
|
|
uint32_t reserved_61; // offset: 61 (0x3D)
|
|
uint32_t reserved_62; // offset: 62 (0x3E)
|
|
uint32_t reserved_63; // offset: 63 (0x3F)
|
|
uint32_t reserved_64; // offset: 64 (0x40)
|
|
uint32_t compute_user_data_0; // offset: 65 (0x41)
|
|
uint32_t compute_user_data_1; // offset: 66 (0x42)
|
|
uint32_t compute_user_data_2; // offset: 67 (0x43)
|
|
uint32_t compute_user_data_3; // offset: 68 (0x44)
|
|
uint32_t compute_user_data_4; // offset: 69 (0x45)
|
|
uint32_t compute_user_data_5; // offset: 70 (0x46)
|
|
uint32_t compute_user_data_6; // offset: 71 (0x47)
|
|
uint32_t compute_user_data_7; // offset: 72 (0x48)
|
|
uint32_t compute_user_data_8; // offset: 73 (0x49)
|
|
uint32_t compute_user_data_9; // offset: 74 (0x4A)
|
|
uint32_t compute_user_data_10; // offset: 75 (0x4B)
|
|
uint32_t compute_user_data_11; // offset: 76 (0x4C)
|
|
uint32_t compute_user_data_12; // offset: 77 (0x4D)
|
|
uint32_t compute_user_data_13; // offset: 78 (0x4E)
|
|
uint32_t compute_user_data_14; // offset: 79 (0x4F)
|
|
uint32_t compute_user_data_15; // offset: 80 (0x50)
|
|
uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51)
|
|
uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52)
|
|
uint32_t reserved_83; // offset: 83 (0x53)
|
|
uint32_t reserved_84; // offset: 84 (0x54)
|
|
uint32_t reserved_85; // offset: 85 (0x55)
|
|
uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)
|
|
uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)
|
|
uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58)
|
|
uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59)
|
|
uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A)
|
|
uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B)
|
|
uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C)
|
|
uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D)
|
|
uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E)
|
|
uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F)
|
|
uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60)
|
|
uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61)
|
|
uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62)
|
|
uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63)
|
|
uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64)
|
|
uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65)
|
|
uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66)
|
|
uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67)
|
|
uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68)
|
|
uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69)
|
|
uint32_t disable_queue; // offset: 106 (0x6A)
|
|
uint32_t reserved_107; // offset: 107 (0x6B)
|
|
uint32_t reserved_108; // offset: 108 (0x6C)
|
|
uint32_t reserved_109; // offset: 109 (0x6D)
|
|
uint32_t reserved_110; // offset: 110 (0x6E)
|
|
uint32_t reserved_111; // offset: 111 (0x6F)
|
|
uint32_t reserved_112; // offset: 112 (0x70)
|
|
uint32_t reserved_113; // offset: 113 (0x71)
|
|
uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72)
|
|
uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73)
|
|
uint32_t cp_packet_id_lo; // offset: 116 (0x74)
|
|
uint32_t cp_packet_id_hi; // offset: 117 (0x75)
|
|
uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76)
|
|
uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77)
|
|
uint32_t reserved_120; // offset: 120 (0x78)
|
|
uint32_t reserved_121; // offset: 121 (0x79)
|
|
uint32_t reserved_122; // offset: 122 (0x7A)
|
|
uint32_t reserved_123; // offset: 123 (0x7B)
|
|
uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C)
|
|
uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D)
|
|
uint32_t reserved_126; // offset: 126 (0x7E)
|
|
uint32_t reserved_127; // offset: 127 (0x7F)
|
|
uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80)
|
|
uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)
|
|
uint32_t cp_hqd_active; // offset: 130 (0x82)
|
|
uint32_t cp_hqd_vmid; // offset: 131 (0x83)
|
|
uint32_t cp_hqd_persistent_state; // offset: 132 (0x84)
|
|
uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85)
|
|
uint32_t cp_hqd_queue_priority; // offset: 134 (0x86)
|
|
uint32_t cp_hqd_quantum; // offset: 135 (0x87)
|
|
uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88)
|
|
uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89)
|
|
uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A)
|
|
uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B)
|
|
uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C)
|
|
uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D)
|
|
uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E)
|
|
uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F)
|
|
uint32_t reserved_144; // offset: 144 (0x90)
|
|
uint32_t cp_hqd_pq_control; // offset: 145 (0x91)
|
|
uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92)
|
|
uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93)
|
|
uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94)
|
|
uint32_t cp_hqd_ib_control; // offset: 149 (0x95)
|
|
uint32_t cp_hqd_iq_timer; // offset: 150 (0x96)
|
|
uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97)
|
|
uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98)
|
|
uint32_t cp_hqd_dma_offload; // offset: 153 (0x99)
|
|
uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A)
|
|
uint32_t cp_hqd_msg_type; // offset: 155 (0x9B)
|
|
uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C)
|
|
uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D)
|
|
uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E)
|
|
uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F)
|
|
uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0)
|
|
uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1)
|
|
uint32_t cp_mqd_control; // offset: 162 (0xA2)
|
|
uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3)
|
|
uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4)
|
|
uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5)
|
|
uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6)
|
|
uint32_t cp_hqd_eop_control; // offset: 167 (0xA7)
|
|
uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8)
|
|
uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9)
|
|
uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA)
|
|
uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB)
|
|
uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC)
|
|
uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD)
|
|
uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE)
|
|
uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF)
|
|
uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0)
|
|
uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1)
|
|
uint32_t reserved_178; // offset: 178 (0xB2)
|
|
uint32_t cp_hqd_error; // offset: 179 (0xB3)
|
|
uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4)
|
|
uint32_t cp_hqd_aql_control; // offset: 181 (0xB5)
|
|
uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6)
|
|
uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7)
|
|
uint32_t reserved_184; // offset: 184 (0xB8)
|
|
uint32_t reserved_185; // offset: 185 (0xB9)
|
|
uint32_t reserved_186; // offset: 186 (0xBA)
|
|
uint32_t reserved_187; // offset: 187 (0xBB)
|
|
uint32_t reserved_188; // offset: 188 (0xBC)
|
|
uint32_t reserved_189; // offset: 189 (0xBD)
|
|
uint32_t reserved_190; // offset: 190 (0xBE)
|
|
uint32_t reserved_191; // offset: 191 (0xBF)
|
|
uint32_t iqtimer_pkt_header; // offset: 192 (0xC0)
|
|
uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1)
|
|
uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2)
|
|
uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3)
|
|
uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4)
|
|
uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5)
|
|
uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6)
|
|
uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7)
|
|
uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8)
|
|
uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9)
|
|
uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA)
|
|
uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB)
|
|
uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC)
|
|
uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD)
|
|
uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE)
|
|
uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF)
|
|
uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0)
|
|
uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1)
|
|
uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2)
|
|
uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3)
|
|
uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4)
|
|
uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5)
|
|
uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6)
|
|
uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7)
|
|
uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8)
|
|
uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9)
|
|
uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA)
|
|
uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB)
|
|
uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC)
|
|
uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD)
|
|
uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE)
|
|
uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF)
|
|
uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0)
|
|
uint32_t reserved_225; // offset: 225 (0xE1)
|
|
uint32_t reserved_226; // offset: 226 (0xE2)
|
|
uint32_t reserved_227; // offset: 227 (0xE3)
|
|
uint32_t set_resources_header; // offset: 228 (0xE4)
|
|
uint32_t set_resources_dw1; // offset: 229 (0xE5)
|
|
uint32_t set_resources_dw2; // offset: 230 (0xE6)
|
|
uint32_t set_resources_dw3; // offset: 231 (0xE7)
|
|
uint32_t set_resources_dw4; // offset: 232 (0xE8)
|
|
uint32_t set_resources_dw5; // offset: 233 (0xE9)
|
|
uint32_t set_resources_dw6; // offset: 234 (0xEA)
|
|
uint32_t set_resources_dw7; // offset: 235 (0xEB)
|
|
uint32_t reserved_236; // offset: 236 (0xEC)
|
|
uint32_t reserved_237; // offset: 237 (0xED)
|
|
uint32_t reserved_238; // offset: 238 (0xEE)
|
|
uint32_t reserved_239; // offset: 239 (0xEF)
|
|
uint32_t queue_doorbell_id0; // offset: 240 (0xF0)
|
|
uint32_t queue_doorbell_id1; // offset: 241 (0xF1)
|
|
uint32_t queue_doorbell_id2; // offset: 242 (0xF2)
|
|
uint32_t queue_doorbell_id3; // offset: 243 (0xF3)
|
|
uint32_t queue_doorbell_id4; // offset: 244 (0xF4)
|
|
uint32_t queue_doorbell_id5; // offset: 245 (0xF5)
|
|
uint32_t queue_doorbell_id6; // offset: 246 (0xF6)
|
|
uint32_t queue_doorbell_id7; // offset: 247 (0xF7)
|
|
uint32_t queue_doorbell_id8; // offset: 248 (0xF8)
|
|
uint32_t queue_doorbell_id9; // offset: 249 (0xF9)
|
|
uint32_t queue_doorbell_id10; // offset: 250 (0xFA)
|
|
uint32_t queue_doorbell_id11; // offset: 251 (0xFB)
|
|
uint32_t queue_doorbell_id12; // offset: 252 (0xFC)
|
|
uint32_t queue_doorbell_id13; // offset: 253 (0xFD)
|
|
uint32_t queue_doorbell_id14; // offset: 254 (0xFE)
|
|
uint32_t queue_doorbell_id15; // offset: 255 (0xFF)
|
|
uint32_t control_buf_addr_lo; // offset: 256 (0x100)
|
|
uint32_t control_buf_addr_hi; // offset: 257 (0x101)
|
|
uint32_t control_buf_wptr_lo; // offset: 258 (0x102)
|
|
uint32_t control_buf_wptr_hi; // offset: 259 (0x103)
|
|
uint32_t control_buf_dptr_lo; // offset: 260 (0x104)
|
|
uint32_t control_buf_dptr_hi; // offset: 261 (0x105)
|
|
uint32_t control_buf_num_entries; // offset: 262 (0x106)
|
|
uint32_t draw_ring_addr_lo; // offset: 263 (0x107)
|
|
uint32_t draw_ring_addr_hi; // offset: 264 (0x108)
|
|
uint32_t reserved_265; // offset: 265 (0x109)
|
|
uint32_t reserved_266; // offset: 266 (0x10A)
|
|
uint32_t reserved_267; // offset: 267 (0x10B)
|
|
uint32_t reserved_268; // offset: 268 (0x10C)
|
|
uint32_t reserved_269; // offset: 269 (0x10D)
|
|
uint32_t reserved_270; // offset: 270 (0x10E)
|
|
uint32_t reserved_271; // offset: 271 (0x10F)
|
|
uint32_t dfwx_flags; // offset: 272 (0x110)
|
|
uint32_t dfwx_slot; // offset: 273 (0x111)
|
|
uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112)
|
|
uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113)
|
|
uint32_t reserved_276; // offset: 276 (0x114)
|
|
uint32_t reserved_277; // offset: 277 (0x115)
|
|
uint32_t reserved_278; // offset: 278 (0x116)
|
|
uint32_t reserved_279; // offset: 279 (0x117)
|
|
uint32_t reserved_280; // offset: 280 (0x118)
|
|
uint32_t reserved_281; // offset: 281 (0x119)
|
|
uint32_t reserved_282; // offset: 282 (0x11A)
|
|
uint32_t reserved_283; // offset: 283 (0x11B)
|
|
uint32_t reserved_284; // offset: 284 (0x11C)
|
|
uint32_t reserved_285; // offset: 285 (0x11D)
|
|
uint32_t reserved_286; // offset: 286 (0x11E)
|
|
uint32_t reserved_287; // offset: 287 (0x11F)
|
|
uint32_t reserved_288; // offset: 288 (0x120)
|
|
uint32_t reserved_289; // offset: 289 (0x121)
|
|
uint32_t reserved_290; // offset: 290 (0x122)
|
|
uint32_t reserved_291; // offset: 291 (0x123)
|
|
uint32_t reserved_292; // offset: 292 (0x124)
|
|
uint32_t reserved_293; // offset: 293 (0x125)
|
|
uint32_t reserved_294; // offset: 294 (0x126)
|
|
uint32_t reserved_295; // offset: 295 (0x127)
|
|
uint32_t reserved_296; // offset: 296 (0x128)
|
|
uint32_t reserved_297; // offset: 297 (0x129)
|
|
uint32_t reserved_298; // offset: 298 (0x12A)
|
|
uint32_t reserved_299; // offset: 299 (0x12B)
|
|
uint32_t reserved_300; // offset: 300 (0x12C)
|
|
uint32_t reserved_301; // offset: 301 (0x12D)
|
|
uint32_t reserved_302; // offset: 302 (0x12E)
|
|
uint32_t reserved_303; // offset: 303 (0x12F)
|
|
uint32_t reserved_304; // offset: 304 (0x130)
|
|
uint32_t reserved_305; // offset: 305 (0x131)
|
|
uint32_t reserved_306; // offset: 306 (0x132)
|
|
uint32_t reserved_307; // offset: 307 (0x133)
|
|
uint32_t reserved_308; // offset: 308 (0x134)
|
|
uint32_t reserved_309; // offset: 309 (0x135)
|
|
uint32_t reserved_310; // offset: 310 (0x136)
|
|
uint32_t reserved_311; // offset: 311 (0x137)
|
|
uint32_t reserved_312; // offset: 312 (0x138)
|
|
uint32_t reserved_313; // offset: 313 (0x139)
|
|
uint32_t reserved_314; // offset: 314 (0x13A)
|
|
uint32_t reserved_315; // offset: 315 (0x13B)
|
|
uint32_t reserved_316; // offset: 316 (0x13C)
|
|
uint32_t reserved_317; // offset: 317 (0x13D)
|
|
uint32_t reserved_318; // offset: 318 (0x13E)
|
|
uint32_t reserved_319; // offset: 319 (0x13F)
|
|
uint32_t reserved_320; // offset: 320 (0x140)
|
|
uint32_t reserved_321; // offset: 321 (0x141)
|
|
uint32_t reserved_322; // offset: 322 (0x142)
|
|
uint32_t reserved_323; // offset: 323 (0x143)
|
|
uint32_t reserved_324; // offset: 324 (0x144)
|
|
uint32_t reserved_325; // offset: 325 (0x145)
|
|
uint32_t reserved_326; // offset: 326 (0x146)
|
|
uint32_t reserved_327; // offset: 327 (0x147)
|
|
uint32_t reserved_328; // offset: 328 (0x148)
|
|
uint32_t reserved_329; // offset: 329 (0x149)
|
|
uint32_t reserved_330; // offset: 330 (0x14A)
|
|
uint32_t reserved_331; // offset: 331 (0x14B)
|
|
uint32_t reserved_332; // offset: 332 (0x14C)
|
|
uint32_t reserved_333; // offset: 333 (0x14D)
|
|
uint32_t reserved_334; // offset: 334 (0x14E)
|
|
uint32_t reserved_335; // offset: 335 (0x14F)
|
|
uint32_t reserved_336; // offset: 336 (0x150)
|
|
uint32_t reserved_337; // offset: 337 (0x151)
|
|
uint32_t reserved_338; // offset: 338 (0x152)
|
|
uint32_t reserved_339; // offset: 339 (0x153)
|
|
uint32_t reserved_340; // offset: 340 (0x154)
|
|
uint32_t reserved_341; // offset: 341 (0x155)
|
|
uint32_t reserved_342; // offset: 342 (0x156)
|
|
uint32_t reserved_343; // offset: 343 (0x157)
|
|
uint32_t reserved_344; // offset: 344 (0x158)
|
|
uint32_t reserved_345; // offset: 345 (0x159)
|
|
uint32_t reserved_346; // offset: 346 (0x15A)
|
|
uint32_t reserved_347; // offset: 347 (0x15B)
|
|
uint32_t reserved_348; // offset: 348 (0x15C)
|
|
uint32_t reserved_349; // offset: 349 (0x15D)
|
|
uint32_t reserved_350; // offset: 350 (0x15E)
|
|
uint32_t reserved_351; // offset: 351 (0x15F)
|
|
uint32_t reserved_352; // offset: 352 (0x160)
|
|
uint32_t reserved_353; // offset: 353 (0x161)
|
|
uint32_t reserved_354; // offset: 354 (0x162)
|
|
uint32_t reserved_355; // offset: 355 (0x163)
|
|
uint32_t reserved_356; // offset: 356 (0x164)
|
|
uint32_t reserved_357; // offset: 357 (0x165)
|
|
uint32_t reserved_358; // offset: 358 (0x166)
|
|
uint32_t reserved_359; // offset: 359 (0x167)
|
|
uint32_t reserved_360; // offset: 360 (0x168)
|
|
uint32_t reserved_361; // offset: 361 (0x169)
|
|
uint32_t reserved_362; // offset: 362 (0x16A)
|
|
uint32_t reserved_363; // offset: 363 (0x16B)
|
|
uint32_t reserved_364; // offset: 364 (0x16C)
|
|
uint32_t reserved_365; // offset: 365 (0x16D)
|
|
uint32_t reserved_366; // offset: 366 (0x16E)
|
|
uint32_t reserved_367; // offset: 367 (0x16F)
|
|
uint32_t reserved_368; // offset: 368 (0x170)
|
|
uint32_t reserved_369; // offset: 369 (0x171)
|
|
uint32_t reserved_370; // offset: 370 (0x172)
|
|
uint32_t reserved_371; // offset: 371 (0x173)
|
|
uint32_t reserved_372; // offset: 372 (0x174)
|
|
uint32_t reserved_373; // offset: 373 (0x175)
|
|
uint32_t reserved_374; // offset: 374 (0x176)
|
|
uint32_t reserved_375; // offset: 375 (0x177)
|
|
uint32_t reserved_376; // offset: 376 (0x178)
|
|
uint32_t reserved_377; // offset: 377 (0x179)
|
|
uint32_t reserved_378; // offset: 378 (0x17A)
|
|
uint32_t reserved_379; // offset: 379 (0x17B)
|
|
uint32_t reserved_380; // offset: 380 (0x17C)
|
|
uint32_t reserved_381; // offset: 381 (0x17D)
|
|
uint32_t reserved_382; // offset: 382 (0x17E)
|
|
uint32_t reserved_383; // offset: 383 (0x17F)
|
|
uint32_t reserved_384; // offset: 384 (0x180)
|
|
uint32_t reserved_385; // offset: 385 (0x181)
|
|
uint32_t reserved_386; // offset: 386 (0x182)
|
|
uint32_t reserved_387; // offset: 387 (0x183)
|
|
uint32_t reserved_388; // offset: 388 (0x184)
|
|
uint32_t reserved_389; // offset: 389 (0x185)
|
|
uint32_t reserved_390; // offset: 390 (0x186)
|
|
uint32_t reserved_391; // offset: 391 (0x187)
|
|
uint32_t reserved_392; // offset: 392 (0x188)
|
|
uint32_t reserved_393; // offset: 393 (0x189)
|
|
uint32_t reserved_394; // offset: 394 (0x18A)
|
|
uint32_t reserved_395; // offset: 395 (0x18B)
|
|
uint32_t reserved_396; // offset: 396 (0x18C)
|
|
uint32_t reserved_397; // offset: 397 (0x18D)
|
|
uint32_t reserved_398; // offset: 398 (0x18E)
|
|
uint32_t reserved_399; // offset: 399 (0x18F)
|
|
uint32_t reserved_400; // offset: 400 (0x190)
|
|
uint32_t reserved_401; // offset: 401 (0x191)
|
|
uint32_t reserved_402; // offset: 402 (0x192)
|
|
uint32_t reserved_403; // offset: 403 (0x193)
|
|
uint32_t reserved_404; // offset: 404 (0x194)
|
|
uint32_t reserved_405; // offset: 405 (0x195)
|
|
uint32_t reserved_406; // offset: 406 (0x196)
|
|
uint32_t reserved_407; // offset: 407 (0x197)
|
|
uint32_t reserved_408; // offset: 408 (0x198)
|
|
uint32_t reserved_409; // offset: 409 (0x199)
|
|
uint32_t reserved_410; // offset: 410 (0x19A)
|
|
uint32_t reserved_411; // offset: 411 (0x19B)
|
|
uint32_t reserved_412; // offset: 412 (0x19C)
|
|
uint32_t reserved_413; // offset: 413 (0x19D)
|
|
uint32_t reserved_414; // offset: 414 (0x19E)
|
|
uint32_t reserved_415; // offset: 415 (0x19F)
|
|
uint32_t reserved_416; // offset: 416 (0x1A0)
|
|
uint32_t reserved_417; // offset: 417 (0x1A1)
|
|
uint32_t reserved_418; // offset: 418 (0x1A2)
|
|
uint32_t reserved_419; // offset: 419 (0x1A3)
|
|
uint32_t reserved_420; // offset: 420 (0x1A4)
|
|
uint32_t reserved_421; // offset: 421 (0x1A5)
|
|
uint32_t reserved_422; // offset: 422 (0x1A6)
|
|
uint32_t reserved_423; // offset: 423 (0x1A7)
|
|
uint32_t reserved_424; // offset: 424 (0x1A8)
|
|
uint32_t reserved_425; // offset: 425 (0x1A9)
|
|
uint32_t reserved_426; // offset: 426 (0x1AA)
|
|
uint32_t reserved_427; // offset: 427 (0x1AB)
|
|
uint32_t reserved_428; // offset: 428 (0x1AC)
|
|
uint32_t reserved_429; // offset: 429 (0x1AD)
|
|
uint32_t reserved_430; // offset: 430 (0x1AE)
|
|
uint32_t reserved_431; // offset: 431 (0x1AF)
|
|
uint32_t reserved_432; // offset: 432 (0x1B0)
|
|
uint32_t reserved_433; // offset: 433 (0x1B1)
|
|
uint32_t reserved_434; // offset: 434 (0x1B2)
|
|
uint32_t reserved_435; // offset: 435 (0x1B3)
|
|
uint32_t reserved_436; // offset: 436 (0x1B4)
|
|
uint32_t reserved_437; // offset: 437 (0x1B5)
|
|
uint32_t reserved_438; // offset: 438 (0x1B6)
|
|
uint32_t reserved_439; // offset: 439 (0x1B7)
|
|
uint32_t reserved_440; // offset: 440 (0x1B8)
|
|
uint32_t reserved_441; // offset: 441 (0x1B9)
|
|
uint32_t reserved_442; // offset: 442 (0x1BA)
|
|
uint32_t reserved_443; // offset: 443 (0x1BB)
|
|
uint32_t reserved_444; // offset: 444 (0x1BC)
|
|
uint32_t reserved_445; // offset: 445 (0x1BD)
|
|
uint32_t fence_address_lo; // offset: 446 (0x1BE)
|
|
uint32_t fence_address_hi; // offset: 447 (0x1BF)
|
|
uint32_t gws_0_val; // offset: 448 (0x1C0)
|
|
uint32_t gws_1_val; // offset: 449 (0x1C1)
|
|
uint32_t gws_2_val; // offset: 450 (0x1C2)
|
|
uint32_t gws_3_val; // offset: 451 (0x1C3)
|
|
uint32_t gws_4_val; // offset: 452 (0x1C4)
|
|
uint32_t gws_5_val; // offset: 453 (0x1C5)
|
|
uint32_t gws_6_val; // offset: 454 (0x1C6)
|
|
uint32_t gws_7_val; // offset: 455 (0x1C7)
|
|
uint32_t gws_8_val; // offset: 456 (0x1C8)
|
|
uint32_t gws_9_val; // offset: 457 (0x1C9)
|
|
uint32_t gws_10_val; // offset: 458 (0x1CA)
|
|
uint32_t gws_11_val; // offset: 459 (0x1CB)
|
|
uint32_t gws_12_val; // offset: 460 (0x1CC)
|
|
uint32_t gws_13_val; // offset: 461 (0x1CD)
|
|
uint32_t gws_14_val; // offset: 462 (0x1CE)
|
|
uint32_t gws_15_val; // offset: 463 (0x1CF)
|
|
uint32_t gws_16_val; // offset: 464 (0x1D0)
|
|
uint32_t gws_17_val; // offset: 465 (0x1D1)
|
|
uint32_t gws_18_val; // offset: 466 (0x1D2)
|
|
uint32_t gws_19_val; // offset: 467 (0x1D3)
|
|
uint32_t gws_20_val; // offset: 468 (0x1D4)
|
|
uint32_t gws_21_val; // offset: 469 (0x1D5)
|
|
uint32_t gws_22_val; // offset: 470 (0x1D6)
|
|
uint32_t gws_23_val; // offset: 471 (0x1D7)
|
|
uint32_t gws_24_val; // offset: 472 (0x1D8)
|
|
uint32_t gws_25_val; // offset: 473 (0x1D9)
|
|
uint32_t gws_26_val; // offset: 474 (0x1DA)
|
|
uint32_t gws_27_val; // offset: 475 (0x1DB)
|
|
uint32_t gws_28_val; // offset: 476 (0x1DC)
|
|
uint32_t gws_29_val; // offset: 477 (0x1DD)
|
|
uint32_t gws_30_val; // offset: 478 (0x1DE)
|
|
uint32_t gws_31_val; // offset: 479 (0x1DF)
|
|
uint32_t gws_32_val; // offset: 480 (0x1E0)
|
|
uint32_t gws_33_val; // offset: 481 (0x1E1)
|
|
uint32_t gws_34_val; // offset: 482 (0x1E2)
|
|
uint32_t gws_35_val; // offset: 483 (0x1E3)
|
|
uint32_t gws_36_val; // offset: 484 (0x1E4)
|
|
uint32_t gws_37_val; // offset: 485 (0x1E5)
|
|
uint32_t gws_38_val; // offset: 486 (0x1E6)
|
|
uint32_t gws_39_val; // offset: 487 (0x1E7)
|
|
uint32_t gws_40_val; // offset: 488 (0x1E8)
|
|
uint32_t gws_41_val; // offset: 489 (0x1E9)
|
|
uint32_t gws_42_val; // offset: 490 (0x1EA)
|
|
uint32_t gws_43_val; // offset: 491 (0x1EB)
|
|
uint32_t gws_44_val; // offset: 492 (0x1EC)
|
|
uint32_t gws_45_val; // offset: 493 (0x1ED)
|
|
uint32_t gws_46_val; // offset: 494 (0x1EE)
|
|
uint32_t gws_47_val; // offset: 495 (0x1EF)
|
|
uint32_t gws_48_val; // offset: 496 (0x1F0)
|
|
uint32_t gws_49_val; // offset: 497 (0x1F1)
|
|
uint32_t gws_50_val; // offset: 498 (0x1F2)
|
|
uint32_t gws_51_val; // offset: 499 (0x1F3)
|
|
uint32_t gws_52_val; // offset: 500 (0x1F4)
|
|
uint32_t gws_53_val; // offset: 501 (0x1F5)
|
|
uint32_t gws_54_val; // offset: 502 (0x1F6)
|
|
uint32_t gws_55_val; // offset: 503 (0x1F7)
|
|
uint32_t gws_56_val; // offset: 504 (0x1F8)
|
|
uint32_t gws_57_val; // offset: 505 (0x1F9)
|
|
uint32_t gws_58_val; // offset: 506 (0x1FA)
|
|
uint32_t gws_59_val; // offset: 507 (0x1FB)
|
|
uint32_t gws_60_val; // offset: 508 (0x1FC)
|
|
uint32_t gws_61_val; // offset: 509 (0x1FD)
|
|
uint32_t gws_62_val; // offset: 510 (0x1FE)
|
|
uint32_t gws_63_val; // offset: 511 (0x1FF)
|
|
};
|
|
|
|
struct v12_1_compute_mqd {
|
|
uint32_t header; // offset: 0 (0x0)
|
|
uint32_t compute_dispatch_initiator; // offset: 1 (0x1)
|
|
uint32_t compute_dim_x; // offset: 2 (0x2)
|
|
uint32_t compute_dim_y; // offset: 3 (0x3)
|
|
uint32_t compute_dim_z; // offset: 4 (0x4)
|
|
uint32_t compute_start_x; // offset: 5 (0x5)
|
|
uint32_t compute_start_y; // offset: 6 (0x6)
|
|
uint32_t compute_start_z; // offset: 7 (0x7)
|
|
uint32_t compute_num_thread_x; // offset: 8 (0x8)
|
|
uint32_t compute_num_thread_y; // offset: 9 (0x9)
|
|
uint32_t compute_num_thread_z; // offset: 10 (0xA)
|
|
uint32_t compute_pipelinestat_enable; // offset: 11 (0xB)
|
|
uint32_t compute_perfcount_enable; // offset: 12 (0xC)
|
|
uint32_t compute_pgm_lo; // offset: 13 (0xD)
|
|
uint32_t compute_pgm_hi; // offset: 14 (0xE)
|
|
uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF)
|
|
uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10)
|
|
uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11)
|
|
uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12)
|
|
uint32_t compute_pgm_rsrc1; // offset: 19 (0x13)
|
|
uint32_t compute_pgm_rsrc2; // offset: 20 (0x14)
|
|
uint32_t compute_vmid; // offset: 21 (0x15)
|
|
uint32_t compute_resource_limits; // offset: 22 (0x16)
|
|
uint32_t compute_tmpring_size; // offset: 23 (0x17)
|
|
uint32_t compute_restart_x; // offset: 24 (0x18)
|
|
uint32_t compute_restart_y; // offset: 25 (0x19)
|
|
uint32_t compute_restart_z; // offset: 26 (0x1A)
|
|
uint32_t compute_thread_trace_enable; // offset: 27 (0x1B)
|
|
uint32_t compute_misc_reserved; // offset: 28 (0x1C)
|
|
uint32_t compute_dispatch_id; // offset: 29 (0x1D)
|
|
uint32_t compute_threadgroup_id; // offset: 30 (0x1E)
|
|
uint32_t compute_req_ctrl; // offset: 31 (0x1F)
|
|
uint32_t compute_user_accum_0; // offset: 32 (0x20)
|
|
uint32_t compute_user_accum_1; // offset: 33 (0x21)
|
|
uint32_t compute_user_accum_2; // offset: 34 (0x22)
|
|
uint32_t compute_user_accum_3; // offset: 35 (0x23)
|
|
uint32_t compute_pgm_rsrc3; // offset: 36 (0x24)
|
|
uint32_t compute_ddid_index; // offset: 37 (0x25)
|
|
uint32_t compute_shader_chksum; // offset: 38 (0x26)
|
|
uint32_t compute_dispatch_interleave; // offset: 39 (0x27)
|
|
uint32_t compute_current_logical_xcc_id; // offset: 40 (0x28)
|
|
uint32_t compute_restart_cg_tg_id; // offset: 41 (0x29)
|
|
uint32_t compute_tg_chunk_size; // offset: 42 (0x2A)
|
|
uint32_t compute_restore_tg_chunk_size; // offset: 43 (0x2B)
|
|
uint32_t reserved_44; // offset: 44 (0x2C)
|
|
uint32_t reserved_45; // offset: 45 (0x2D)
|
|
uint32_t compute_prescaled_dim_x; // offset: 46 (0x2E)
|
|
uint32_t compute_prescaled_dim_y; // offset: 47 (0x2F)
|
|
uint32_t compute_prescaled_dim_z; // offset: 48 (0x30)
|
|
uint32_t compute_static_thread_mgmt_se0; // offset: 49 (0x31)
|
|
uint32_t compute_static_thread_mgmt_se1; // offset: 50 (0x32)
|
|
uint32_t compute_static_thread_mgmt_se2; // offset: 51 (0x33)
|
|
uint32_t compute_static_thread_mgmt_se3; // offset: 52 (0x34)
|
|
uint32_t compute_static_thread_mgmt_se4; // offset: 53 (0x35)
|
|
uint32_t compute_static_thread_mgmt_se5; // offset: 54 (0x36)
|
|
uint32_t compute_static_thread_mgmt_se6; // offset: 55 (0x37)
|
|
uint32_t compute_static_thread_mgmt_se7; // offset: 56 (0x38)
|
|
uint32_t compute_static_thread_mgmt_se8; // offset: 57 (0x39)
|
|
uint32_t reserved_58; // offset: 58 (0x3A)
|
|
uint32_t reserved_59; // offset: 59 (0x3B)
|
|
uint32_t reserved_60; // offset: 60 (0x3C)
|
|
uint32_t reserved_61; // offset: 61 (0x3D)
|
|
uint32_t reserved_62; // offset: 62 (0x3E)
|
|
uint32_t reserved_63; // offset: 63 (0x3F)
|
|
uint32_t tg_counter_id; // offset: 64 (0x40)
|
|
uint32_t compute_user_data_0; // offset: 65 (0x41)
|
|
uint32_t compute_user_data_1; // offset: 66 (0x42)
|
|
uint32_t compute_user_data_2; // offset: 67 (0x43)
|
|
uint32_t compute_user_data_3; // offset: 68 (0x44)
|
|
uint32_t compute_user_data_4; // offset: 69 (0x45)
|
|
uint32_t compute_user_data_5; // offset: 70 (0x46)
|
|
uint32_t compute_user_data_6; // offset: 71 (0x47)
|
|
uint32_t compute_user_data_7; // offset: 72 (0x48)
|
|
uint32_t compute_user_data_8; // offset: 73 (0x49)
|
|
uint32_t compute_user_data_9; // offset: 74 (0x4A)
|
|
uint32_t compute_user_data_10; // offset: 75 (0x4B)
|
|
uint32_t compute_user_data_11; // offset: 76 (0x4C)
|
|
uint32_t compute_user_data_12; // offset: 77 (0x4D)
|
|
uint32_t compute_user_data_13; // offset: 78 (0x4E)
|
|
uint32_t compute_user_data_14; // offset: 79 (0x4F)
|
|
uint32_t compute_user_data_15; // offset: 80 (0x50)
|
|
uint32_t compute_user_data_16; // offset: 81 (0x51)
|
|
uint32_t compute_user_data_17; // offset: 82 (0x52)
|
|
uint32_t compute_user_data_18; // offset: 83 (0x53)
|
|
uint32_t compute_user_data_19; // offset: 84 (0x54)
|
|
uint32_t compute_user_data_20; // offset: 85 (0x55)
|
|
uint32_t compute_user_data_21; // offset: 86 (0x56)
|
|
uint32_t compute_user_data_22; // offset: 87 (0x57)
|
|
uint32_t compute_user_data_23; // offset: 88 (0x58)
|
|
uint32_t compute_user_data_24; // offset: 89 (0x59)
|
|
uint32_t compute_user_data_25; // offset: 90 (0x5A)
|
|
uint32_t compute_user_data_26; // offset: 91 (0x5B)
|
|
uint32_t compute_user_data_27; // offset: 92 (0x5C)
|
|
uint32_t compute_user_data_28; // offset: 93 (0x5D)
|
|
uint32_t compute_user_data_29; // offset: 94 (0x5E)
|
|
uint32_t compute_user_data_30; // offset: 95 (0x5F)
|
|
uint32_t compute_user_data_31; // offset: 96 (0x60)
|
|
uint32_t cp_compute_csinvoc_count_lo; // offset: 97 (0x61)
|
|
uint32_t cp_compute_csinvoc_count_hi; // offset: 98 (0x62)
|
|
uint32_t reserved_99; // offset: 99 (0x63)
|
|
uint32_t reserved_100; // offset: 100 (0x64)
|
|
uint32_t reserved_101; // offset: 101 (0x65)
|
|
uint32_t reserved_102; // offset: 102 (0x66)
|
|
uint32_t reserved_103; // offset: 103 (0x67)
|
|
uint32_t reserved_104; // offset: 104 (0x68)
|
|
uint32_t reserved_105; // offset: 105 (0x69)
|
|
uint32_t reserved_106; // offset: 106 (0x6A)
|
|
uint32_t reserved_107; // offset: 107 (0x6B)
|
|
uint32_t reserved_108; // offset: 108 (0x6C)
|
|
uint32_t reserved_109; // offset: 109 (0x6D)
|
|
uint32_t compute_relaunch; // offset: 110 (0x6E)
|
|
uint32_t compute_wave_restore_addr_lo; // offset: 111 (0x6F)
|
|
uint32_t compute_wave_restore_addr_hi; // offset: 112 (0x70)
|
|
uint32_t compute_relaunch2; // offset: 113 (0x71)
|
|
uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72)
|
|
uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73)
|
|
uint32_t cp_packet_id_lo; // offset: 116 (0x74)
|
|
uint32_t cp_packet_id_hi; // offset: 117 (0x75)
|
|
uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76)
|
|
uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77)
|
|
uint32_t reserved_120; // offset: 120 (0x78)
|
|
uint32_t reserved_121; // offset: 121 (0x79)
|
|
uint32_t reserved_122; // offset: 122 (0x7A)
|
|
uint32_t reserved_123; // offset: 123 (0x7B)
|
|
uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C)
|
|
uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D)
|
|
uint32_t reserved_126; // offset: 126 (0x7E)
|
|
uint32_t reserved_127; // offset: 127 (0x7F)
|
|
uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80)
|
|
uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)
|
|
uint32_t cp_hqd_active; // offset: 130 (0x82)
|
|
uint32_t cp_hqd_vmid; // offset: 131 (0x83)
|
|
uint32_t cp_hqd_persistent_state; // offset: 132 (0x84)
|
|
uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85)
|
|
uint32_t cp_hqd_queue_priority; // offset: 134 (0x86)
|
|
uint32_t cp_hqd_quantum; // offset: 135 (0x87)
|
|
uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88)
|
|
uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89)
|
|
uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A)
|
|
uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B)
|
|
uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C)
|
|
uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D)
|
|
uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E)
|
|
uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F)
|
|
uint32_t reserved_144; // offset: 144 (0x90)
|
|
uint32_t cp_hqd_pq_control; // offset: 145 (0x91)
|
|
uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92)
|
|
uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93)
|
|
uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94)
|
|
uint32_t cp_hqd_ib_control; // offset: 149 (0x95)
|
|
uint32_t cp_hqd_iq_timer; // offset: 150 (0x96)
|
|
uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97)
|
|
uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98)
|
|
uint32_t cp_hqd_dma_offload; // offset: 153 (0x99)
|
|
uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A)
|
|
uint32_t cp_hqd_msg_type; // offset: 155 (0x9B)
|
|
uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C)
|
|
uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D)
|
|
uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E)
|
|
uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F)
|
|
uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0)
|
|
uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1)
|
|
uint32_t cp_mqd_control; // offset: 162 (0xA2)
|
|
uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3)
|
|
uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4)
|
|
uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5)
|
|
uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6)
|
|
uint32_t cp_hqd_eop_control; // offset: 167 (0xA7)
|
|
uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8)
|
|
uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9)
|
|
uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA)
|
|
uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB)
|
|
uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC)
|
|
uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD)
|
|
uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE)
|
|
uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF)
|
|
uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0)
|
|
uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1)
|
|
uint32_t reserved_178; // offset: 178 (0xB2)
|
|
uint32_t cp_hqd_error; // offset: 179 (0xB3)
|
|
uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4)
|
|
uint32_t cp_hqd_aql_control; // offset: 181 (0xB5)
|
|
uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6)
|
|
uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7)
|
|
uint32_t cp_hqd_suspend_cntl_stack_offset; // offset: 184 (0xB8)
|
|
uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; // offset: 185 (0xB9)
|
|
uint32_t cp_hqd_suspend_wg_state_offset; // offset: 186 (0xBA)
|
|
uint32_t cp_hqd_ddid_rptr; // offset: 187 (0xBB)
|
|
uint32_t cp_hqd_ddid_wptr; // offset: 188 (0xBC)
|
|
uint32_t cp_hqd_ddid_inflight_count; // offset: 189 (0xBD)
|
|
uint32_t cp_hqd_ddid_delta_rpt_count; // offset: 190 (0xBE)
|
|
uint32_t cp_hqd_dequeue_status; // offset: 191 (0xBF)
|
|
uint32_t cp_hqd_aql_control_1; // offset: 192 (0xC0)
|
|
uint32_t cp_hqd_aql_dispatch_id; // offset: 193 (0xC1)
|
|
uint32_t cp_hqd_aql_dispatch_id_hi; // offset: 194 (0xC2)
|
|
uint32_t cp_hqd_kd_base; // offset: 195 (0xC3)
|
|
uint32_t cp_hqd_kd_base_hi; // offset: 196 (0xC4)
|
|
uint32_t cp_hqd_kd_cntl; // offset: 197 (0xC5)
|
|
uint32_t reserved_198; // offset: 198 (0xC6)
|
|
uint32_t reserved_199; // offset: 199 (0xC7)
|
|
uint32_t reserved_200; // offset: 200 (0xC8)
|
|
uint32_t reserved_201; // offset: 201 (0xC9)
|
|
uint32_t reserved_202; // offset: 202 (0xCA)
|
|
uint32_t reserved_203; // offset: 203 (0xCB)
|
|
uint32_t reserved_204; // offset: 204 (0xCC)
|
|
uint32_t reserved_205; // offset: 205 (0xCD)
|
|
uint32_t reserved_206; // offset: 206 (0xCE)
|
|
uint32_t reserved_207; // offset: 207 (0xCF)
|
|
uint32_t reserved_208; // offset: 208 (0xD0)
|
|
uint32_t reserved_209; // offset: 209 (0xD1)
|
|
uint32_t reserved_210; // offset: 210 (0xD2)
|
|
uint32_t reserved_211; // offset: 211 (0xD3)
|
|
uint32_t reserved_212; // offset: 212 (0xD4)
|
|
uint32_t reserved_213; // offset: 213 (0xD5)
|
|
uint32_t reserved_214; // offset: 214 (0xD6)
|
|
uint32_t reserved_215; // offset: 215 (0xD7)
|
|
uint32_t reserved_216; // offset: 216 (0xD8)
|
|
uint32_t reserved_217; // offset: 217 (0xD9)
|
|
uint32_t reserved_218; // offset: 218 (0xDA)
|
|
uint32_t reserved_219; // offset: 219 (0xDB)
|
|
uint32_t reserved_220; // offset: 220 (0xDC)
|
|
uint32_t reserved_221; // offset: 221 (0xDD)
|
|
uint32_t reserved_222; // offset: 222 (0xDE)
|
|
uint32_t reserved_223; // offset: 223 (0xDF)
|
|
uint32_t reserved_224; // offset: 224 (0xE0)
|
|
uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1)
|
|
uint32_t cp_mqd_stride_size; // offset: 226 (0xE2)
|
|
uint32_t xcc_sync_counter; // offset: 227 (0xE3)
|
|
uint32_t set_resources_header; // offset: 228 (0xE4)
|
|
uint32_t set_resources_dw1; // offset: 229 (0xE5)
|
|
uint32_t set_resources_dw2; // offset: 230 (0xE6)
|
|
uint32_t set_resources_dw3; // offset: 231 (0xE7)
|
|
uint32_t set_resources_dw4; // offset: 232 (0xE8)
|
|
uint32_t set_resources_dw5; // offset: 233 (0xE9)
|
|
uint32_t set_resources_dw6; // offset: 234 (0xEA)
|
|
uint32_t set_resources_dw7; // offset: 235 (0xEB)
|
|
uint32_t reserved_236; // offset: 236 (0xEC)
|
|
uint32_t reserved_237; // offset: 237 (0xED)
|
|
uint32_t reserved_238; // offset: 238 (0xEE)
|
|
uint32_t reserved_239; // offset: 239 (0xEF)
|
|
uint32_t reserved_240; // offset: 240 (0xF0)
|
|
uint32_t reserved_241; // offset: 241 (0xF1)
|
|
uint32_t reserved_242; // offset: 242 (0xF2)
|
|
uint32_t reserved_243; // offset: 243 (0xF3)
|
|
uint32_t reserved_244; // offset: 244 (0xF4)
|
|
uint32_t reserved_245; // offset: 245 (0xF5)
|
|
uint32_t reserved_246; // offset: 246 (0xF6)
|
|
uint32_t reserved_247; // offset: 247 (0xF7)
|
|
uint32_t reserved_248; // offset: 248 (0xF8)
|
|
uint32_t reserved_249; // offset: 249 (0xF9)
|
|
uint32_t reserved_250; // offset: 250 (0xFA)
|
|
uint32_t reserved_251; // offset: 251 (0xFB)
|
|
uint32_t reserved_252; // offset: 252 (0xFC)
|
|
uint32_t reserved_253; // offset: 253 (0xFD)
|
|
uint32_t reserved_254; // offset: 254 (0xFE)
|
|
uint32_t reserved_255; // offset: 255 (0xFF)
|
|
uint32_t control_buf_addr_lo; // offset: 256 (0x100)
|
|
uint32_t control_buf_addr_hi; // offset: 257 (0x101)
|
|
uint32_t control_buf_wptr_lo; // offset: 258 (0x102)
|
|
uint32_t control_buf_wptr_hi; // offset: 259 (0x103)
|
|
uint32_t control_buf_dptr_lo; // offset: 260 (0x104)
|
|
uint32_t control_buf_dptr_hi; // offset: 261 (0x105)
|
|
uint32_t draw_ring_addr_lo; // offset: 262 (0x106)
|
|
uint32_t draw_ring_addr_hi; // offset: 263 (0x107)
|
|
uint32_t control_buf_num_entries; // offset: 264 (0x108)
|
|
uint32_t reserved_265; // offset: 265 (0x109)
|
|
uint32_t reserved_266; // offset: 266 (0x10A)
|
|
uint32_t reserved_267; // offset: 267 (0x10B)
|
|
uint32_t reserved_268; // offset: 268 (0x10C)
|
|
uint32_t reserved_269; // offset: 269 (0x10D)
|
|
uint32_t reserved_270; // offset: 270 (0x10E)
|
|
uint32_t reserved_271; // offset: 271 (0x10F)
|
|
uint32_t dfwx_flags; // offset: 272 (0x110)
|
|
uint32_t dfwx_slot; // offset: 273 (0x111)
|
|
uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112)
|
|
uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113)
|
|
uint32_t dfwx_queue_connect_addr_lo; // offset: 276 (0x114)
|
|
uint32_t dfwx_queue_connect_addr_hi; // offset: 277 (0x115)
|
|
uint32_t reserved_278; // offset: 278 (0x116)
|
|
uint32_t reserved_279; // offset: 279 (0x117)
|
|
uint32_t reserved_280; // offset: 280 (0x118)
|
|
uint32_t reserved_281; // offset: 281 (0x119)
|
|
uint32_t reserved_282; // offset: 282 (0x11A)
|
|
uint32_t reserved_283; // offset: 283 (0x11B)
|
|
uint32_t reserved_284; // offset: 284 (0x11C)
|
|
uint32_t reserved_285; // offset: 285 (0x11D)
|
|
uint32_t reserved_286; // offset: 286 (0x11E)
|
|
uint32_t reserved_287; // offset: 287 (0x11F)
|
|
uint32_t cp_mqd_query_time_lo; // offset: 288 (0x120)
|
|
uint32_t cp_mqd_query_time_hi; // offset: 289 (0x121)
|
|
uint32_t cp_mqd_connect_start_time_lo; // offset: 290 (0x122)
|
|
uint32_t cp_mqd_connect_start_time_hi; // offset: 291 (0x123)
|
|
uint32_t cp_mqd_connect_end_time_lo; // offset: 292 (0x124)
|
|
uint32_t cp_mqd_connect_end_time_hi; // offset: 293 (0x125)
|
|
uint32_t cp_mqd_connect_end_wf_count; // offset: 294 (0x126)
|
|
uint32_t cp_mqd_connect_end_pq_rptr; // offset: 295 (0x127)
|
|
uint32_t cp_mqd_connect_end_pq_wptr; // offset: 296 (0x128)
|
|
uint32_t cp_mqd_connect_end_ib_rptr; // offset: 297 (0x129)
|
|
uint32_t cp_mqd_readindex_lo; // offset: 298 (0x12A)
|
|
uint32_t cp_mqd_readindex_hi; // offset: 299 (0x12B)
|
|
uint32_t cp_mqd_save_start_time_lo; // offset: 300 (0x12C)
|
|
uint32_t cp_mqd_save_start_time_hi; // offset: 301 (0x12D)
|
|
uint32_t cp_mqd_save_end_time_lo; // offset: 302 (0x12E)
|
|
uint32_t cp_mqd_save_end_time_hi; // offset: 303 (0x12F)
|
|
uint32_t cp_mqd_restore_start_time_lo; // offset: 304 (0x130)
|
|
uint32_t cp_mqd_restore_start_time_hi; // offset: 305 (0x131)
|
|
uint32_t cp_mqd_restore_end_time_lo; // offset: 306 (0x132)
|
|
uint32_t cp_mqd_restore_end_time_hi; // offset: 307 (0x133)
|
|
uint32_t disable_queue; // offset: 308 (0x134)
|
|
uint32_t reserved_309; // offset: 309 (0x135)
|
|
uint32_t reserved_310; // offset: 310 (0x136)
|
|
uint32_t reserved_311; // offset: 311 (0x137)
|
|
uint32_t reserved_312; // offset: 312 (0x138)
|
|
uint32_t reserved_313; // offset: 313 (0x139)
|
|
uint32_t reserved_314; // offset: 314 (0x13A)
|
|
uint32_t reserved_315; // offset: 315 (0x13B)
|
|
uint32_t reserved_316; // offset: 316 (0x13C)
|
|
uint32_t reserved_317; // offset: 317 (0x13D)
|
|
uint32_t reserved_318; // offset: 318 (0x13E)
|
|
uint32_t reserved_319; // offset: 319 (0x13F)
|
|
uint32_t reserved_320; // offset: 320 (0x140)
|
|
uint32_t reserved_321; // offset: 321 (0x141)
|
|
uint32_t reserved_322; // offset: 322 (0x142)
|
|
uint32_t reserved_323; // offset: 323 (0x143)
|
|
uint32_t reserved_324; // offset: 324 (0x144)
|
|
uint32_t reserved_325; // offset: 325 (0x145)
|
|
uint32_t reserved_326; // offset: 326 (0x146)
|
|
uint32_t reserved_327; // offset: 327 (0x147)
|
|
uint32_t reserved_328; // offset: 328 (0x148)
|
|
uint32_t reserved_329; // offset: 329 (0x149)
|
|
uint32_t reserved_330; // offset: 330 (0x14A)
|
|
uint32_t reserved_331; // offset: 331 (0x14B)
|
|
uint32_t reserved_332; // offset: 332 (0x14C)
|
|
uint32_t reserved_333; // offset: 333 (0x14D)
|
|
uint32_t reserved_334; // offset: 334 (0x14E)
|
|
uint32_t reserved_335; // offset: 335 (0x14F)
|
|
uint32_t reserved_336; // offset: 336 (0x150)
|
|
uint32_t reserved_337; // offset: 337 (0x151)
|
|
uint32_t reserved_338; // offset: 338 (0x152)
|
|
uint32_t reserved_339; // offset: 339 (0x153)
|
|
uint32_t reserved_340; // offset: 340 (0x154)
|
|
uint32_t reserved_341; // offset: 341 (0x155)
|
|
uint32_t reserved_342; // offset: 342 (0x156)
|
|
uint32_t reserved_343; // offset: 343 (0x157)
|
|
uint32_t reserved_344; // offset: 344 (0x158)
|
|
uint32_t reserved_345; // offset: 345 (0x159)
|
|
uint32_t reserved_346; // offset: 346 (0x15A)
|
|
uint32_t reserved_347; // offset: 347 (0x15B)
|
|
uint32_t reserved_348; // offset: 348 (0x15C)
|
|
uint32_t reserved_349; // offset: 349 (0x15D)
|
|
uint32_t reserved_350; // offset: 350 (0x15E)
|
|
uint32_t reserved_351; // offset: 351 (0x15F)
|
|
uint32_t reserved_352; // offset: 352 (0x160)
|
|
uint32_t reserved_353; // offset: 353 (0x161)
|
|
uint32_t reserved_354; // offset: 354 (0x162)
|
|
uint32_t reserved_355; // offset: 355 (0x163)
|
|
uint32_t reserved_356; // offset: 356 (0x164)
|
|
uint32_t reserved_357; // offset: 357 (0x165)
|
|
uint32_t reserved_358; // offset: 358 (0x166)
|
|
uint32_t reserved_359; // offset: 359 (0x167)
|
|
uint32_t reserved_360; // offset: 360 (0x168)
|
|
uint32_t reserved_361; // offset: 361 (0x169)
|
|
uint32_t reserved_362; // offset: 362 (0x16A)
|
|
uint32_t reserved_363; // offset: 363 (0x16B)
|
|
uint32_t reserved_364; // offset: 364 (0x16C)
|
|
uint32_t reserved_365; // offset: 365 (0x16D)
|
|
uint32_t reserved_366; // offset: 366 (0x16E)
|
|
uint32_t reserved_367; // offset: 367 (0x16F)
|
|
uint32_t reserved_368; // offset: 368 (0x170)
|
|
uint32_t reserved_369; // offset: 369 (0x171)
|
|
uint32_t reserved_370; // offset: 370 (0x172)
|
|
uint32_t reserved_371; // offset: 371 (0x173)
|
|
uint32_t reserved_372; // offset: 372 (0x174)
|
|
uint32_t reserved_373; // offset: 373 (0x175)
|
|
uint32_t reserved_374; // offset: 374 (0x176)
|
|
uint32_t reserved_375; // offset: 375 (0x177)
|
|
uint32_t reserved_376; // offset: 376 (0x178)
|
|
uint32_t reserved_377; // offset: 377 (0x179)
|
|
uint32_t reserved_378; // offset: 378 (0x17A)
|
|
uint32_t reserved_379; // offset: 379 (0x17B)
|
|
uint32_t reserved_380; // offset: 380 (0x17C)
|
|
uint32_t reserved_381; // offset: 381 (0x17D)
|
|
uint32_t reserved_382; // offset: 382 (0x17E)
|
|
uint32_t reserved_383; // offset: 383 (0x17F)
|
|
uint32_t iqtimer_pkt_header; // offset: 384 (0x180)
|
|
uint32_t iqtimer_pkt_dw0; // offset: 385 (0x181)
|
|
uint32_t iqtimer_pkt_dw1; // offset: 386 (0x182)
|
|
uint32_t iqtimer_pkt_dw2; // offset: 387 (0x183)
|
|
uint32_t iqtimer_pkt_dw3; // offset: 388 (0x184)
|
|
uint32_t iqtimer_pkt_dw4; // offset: 389 (0x185)
|
|
uint32_t iqtimer_pkt_dw5; // offset: 390 (0x186)
|
|
uint32_t iqtimer_pkt_dw6; // offset: 391 (0x187)
|
|
uint32_t iqtimer_pkt_dw7; // offset: 392 (0x188)
|
|
uint32_t iqtimer_pkt_dw8; // offset: 393 (0x189)
|
|
uint32_t iqtimer_pkt_dw9; // offset: 394 (0x18A)
|
|
uint32_t iqtimer_pkt_dw10; // offset: 395 (0x18B)
|
|
uint32_t iqtimer_pkt_dw11; // offset: 396 (0x18C)
|
|
uint32_t iqtimer_pkt_dw12; // offset: 397 (0x18D)
|
|
uint32_t iqtimer_pkt_dw13; // offset: 398 (0x18E)
|
|
uint32_t iqtimer_pkt_dw14; // offset: 399 (0x18F)
|
|
uint32_t iqtimer_pkt_dw15; // offset: 400 (0x190)
|
|
uint32_t iqtimer_pkt_dw16; // offset: 401 (0x191)
|
|
uint32_t iqtimer_pkt_dw17; // offset: 402 (0x192)
|
|
uint32_t iqtimer_pkt_dw18; // offset: 403 (0x193)
|
|
uint32_t iqtimer_pkt_dw19; // offset: 404 (0x194)
|
|
uint32_t iqtimer_pkt_dw20; // offset: 405 (0x195)
|
|
uint32_t iqtimer_pkt_dw21; // offset: 406 (0x196)
|
|
uint32_t iqtimer_pkt_dw22; // offset: 407 (0x197)
|
|
uint32_t iqtimer_pkt_dw23; // offset: 408 (0x198)
|
|
uint32_t iqtimer_pkt_dw24; // offset: 409 (0x199)
|
|
uint32_t iqtimer_pkt_dw25; // offset: 410 (0x19A)
|
|
uint32_t iqtimer_pkt_dw26; // offset: 411 (0x19B)
|
|
uint32_t iqtimer_pkt_dw27; // offset: 412 (0x19C)
|
|
uint32_t iqtimer_pkt_dw28; // offset: 413 (0x19D)
|
|
uint32_t iqtimer_pkt_dw29; // offset: 414 (0x19E)
|
|
uint32_t iqtimer_pkt_dw30; // offset: 415 (0x19F)
|
|
uint32_t iqtimer_pkt_dw31; // offset: 416 (0x1A0)
|
|
uint32_t reserved_417; // offset: 417 (0x1A1)
|
|
uint32_t reserved_418; // offset: 418 (0x1A2)
|
|
uint32_t reserved_419; // offset: 419 (0x1A3)
|
|
uint32_t reserved_420; // offset: 420 (0x1A4)
|
|
uint32_t reserved_421; // offset: 421 (0x1A5)
|
|
uint32_t reserved_422; // offset: 422 (0x1A6)
|
|
uint32_t reserved_423; // offset: 423 (0x1A7)
|
|
uint32_t reserved_424; // offset: 424 (0x1A8)
|
|
uint32_t reserved_425; // offset: 425 (0x1A9)
|
|
uint32_t reserved_426; // offset: 426 (0x1AA)
|
|
uint32_t reserved_427; // offset: 427 (0x1AB)
|
|
uint32_t reserved_428; // offset: 428 (0x1AC)
|
|
uint32_t reserved_429; // offset: 429 (0x1AD)
|
|
uint32_t reserved_430; // offset: 430 (0x1AE)
|
|
uint32_t reserved_431; // offset: 431 (0x1AF)
|
|
uint32_t reserved_432; // offset: 432 (0x1B0)
|
|
uint32_t reserved_433; // offset: 433 (0x1B1)
|
|
uint32_t reserved_434; // offset: 434 (0x1B2)
|
|
uint32_t reserved_435; // offset: 435 (0x1B3)
|
|
uint32_t reserved_436; // offset: 436 (0x1B4)
|
|
uint32_t reserved_437; // offset: 437 (0x1B5)
|
|
uint32_t reserved_438; // offset: 438 (0x1B6)
|
|
uint32_t reserved_439; // offset: 439 (0x1B7)
|
|
uint32_t reserved_440; // offset: 440 (0x1B8)
|
|
uint32_t reserved_441; // offset: 441 (0x1B9)
|
|
uint32_t reserved_442; // offset: 442 (0x1BA)
|
|
uint32_t reserved_443; // offset: 443 (0x1BB)
|
|
uint32_t reserved_444; // offset: 444 (0x1BC)
|
|
uint32_t reserved_445; // offset: 445 (0x1BD)
|
|
uint32_t reserved_446; // offset: 446 (0x1BE)
|
|
uint32_t reserved_447; // offset: 447 (0x1BF)
|
|
uint32_t reserved_448; // offset: 448 (0x1C0)
|
|
uint32_t reserved_449; // offset: 449 (0x1C1)
|
|
uint32_t reserved_450; // offset: 450 (0x1C2)
|
|
uint32_t reserved_451; // offset: 451 (0x1C3)
|
|
uint32_t reserved_452; // offset: 452 (0x1C4)
|
|
uint32_t reserved_453; // offset: 453 (0x1C5)
|
|
uint32_t reserved_454; // offset: 454 (0x1C6)
|
|
uint32_t reserved_455; // offset: 455 (0x1C7)
|
|
uint32_t reserved_456; // offset: 456 (0x1C8)
|
|
uint32_t reserved_457; // offset: 457 (0x1C9)
|
|
uint32_t reserved_458; // offset: 458 (0x1CA)
|
|
uint32_t reserved_459; // offset: 459 (0x1CB)
|
|
uint32_t reserved_460; // offset: 460 (0x1CC)
|
|
uint32_t reserved_461; // offset: 461 (0x1CD)
|
|
uint32_t reserved_462; // offset: 462 (0x1CE)
|
|
uint32_t reserved_463; // offset: 463 (0x1CF)
|
|
uint32_t reserved_464; // offset: 464 (0x1D0)
|
|
uint32_t reserved_465; // offset: 465 (0x1D1)
|
|
uint32_t reserved_466; // offset: 466 (0x1D2)
|
|
uint32_t reserved_467; // offset: 467 (0x1D3)
|
|
uint32_t reserved_468; // offset: 468 (0x1D4)
|
|
uint32_t reserved_469; // offset: 469 (0x1D5)
|
|
uint32_t reserved_470; // offset: 470 (0x1D6)
|
|
uint32_t reserved_471; // offset: 471 (0x1D7)
|
|
uint32_t reserved_472; // offset: 472 (0x1D8)
|
|
uint32_t reserved_473; // offset: 473 (0x1D9)
|
|
uint32_t reserved_474; // offset: 474 (0x1DA)
|
|
uint32_t reserved_475; // offset: 475 (0x1DB)
|
|
uint32_t reserved_476; // offset: 476 (0x1DC)
|
|
uint32_t reserved_477; // offset: 477 (0x1DD)
|
|
uint32_t reserved_478; // offset: 478 (0x1DE)
|
|
uint32_t reserved_479; // offset: 479 (0x1DF)
|
|
uint32_t reserved_480; // offset: 480 (0x1E0)
|
|
uint32_t reserved_481; // offset: 481 (0x1E1)
|
|
uint32_t reserved_482; // offset: 482 (0x1E2)
|
|
uint32_t reserved_483; // offset: 483 (0x1E3)
|
|
uint32_t reserved_484; // offset: 484 (0x1E4)
|
|
uint32_t reserved_485; // offset: 485 (0x1E5)
|
|
uint32_t reserved_486; // offset: 486 (0x1E6)
|
|
uint32_t reserved_487; // offset: 487 (0x1E7)
|
|
uint32_t reserved_488; // offset: 488 (0x1E8)
|
|
uint32_t reserved_489; // offset: 489 (0x1E9)
|
|
uint32_t reserved_490; // offset: 490 (0x1EA)
|
|
uint32_t reserved_491; // offset: 491 (0x1EB)
|
|
uint32_t reserved_492; // offset: 492 (0x1EC)
|
|
uint32_t reserved_493; // offset: 493 (0x1ED)
|
|
uint32_t reserved_494; // offset: 494 (0x1EE)
|
|
uint32_t reserved_495; // offset: 495 (0x1EF)
|
|
uint32_t reserved_496; // offset: 496 (0x1F0)
|
|
uint32_t reserved_497; // offset: 497 (0x1F1)
|
|
uint32_t reserved_498; // offset: 498 (0x1F2)
|
|
uint32_t reserved_499; // offset: 499 (0x1F3)
|
|
uint32_t reserved_500; // offset: 500 (0x1F4)
|
|
uint32_t reserved_501; // offset: 501 (0x1F5)
|
|
uint32_t reserved_502; // offset: 502 (0x1F6)
|
|
uint32_t reserved_503; // offset: 503 (0x1F7)
|
|
uint32_t reserved_504; // offset: 504 (0x1F8)
|
|
uint32_t reserved_505; // offset: 505 (0x1F9)
|
|
uint32_t reserved_506; // offset: 506 (0x1FA)
|
|
uint32_t reserved_507; // offset: 507 (0x1FB)
|
|
uint32_t reserved_508; // offset: 508 (0x1FC)
|
|
uint32_t reserved_509; // offset: 509 (0x1FD)
|
|
uint32_t reserved_510; // offset: 510 (0x1FE)
|
|
uint32_t reserved_511; // offset: 511 (0x1FF)
|
|
uint32_t reserved_512; // offset: 512 (0x200)
|
|
uint32_t reserved_513; // offset: 513 (0x201)
|
|
uint32_t reserved_514; // offset: 514 (0x202)
|
|
uint32_t reserved_515; // offset: 515 (0x203)
|
|
uint32_t reserved_516; // offset: 516 (0x204)
|
|
uint32_t reserved_517; // offset: 517 (0x205)
|
|
uint32_t reserved_518; // offset: 518 (0x206)
|
|
uint32_t reserved_519; // offset: 519 (0x207)
|
|
uint32_t reserved_520; // offset: 520 (0x208)
|
|
uint32_t reserved_521; // offset: 521 (0x209)
|
|
uint32_t reserved_522; // offset: 522 (0x20A)
|
|
uint32_t reserved_523; // offset: 523 (0x20B)
|
|
uint32_t reserved_524; // offset: 524 (0x20C)
|
|
uint32_t reserved_525; // offset: 525 (0x20D)
|
|
uint32_t reserved_526; // offset: 526 (0x20E)
|
|
uint32_t reserved_527; // offset: 527 (0x20F)
|
|
uint32_t reserved_528; // offset: 528 (0x210)
|
|
uint32_t reserved_529; // offset: 529 (0x211)
|
|
uint32_t reserved_530; // offset: 530 (0x212)
|
|
uint32_t reserved_531; // offset: 531 (0x213)
|
|
uint32_t reserved_532; // offset: 532 (0x214)
|
|
uint32_t reserved_533; // offset: 533 (0x215)
|
|
uint32_t reserved_534; // offset: 534 (0x216)
|
|
uint32_t reserved_535; // offset: 535 (0x217)
|
|
uint32_t reserved_536; // offset: 536 (0x218)
|
|
uint32_t reserved_537; // offset: 537 (0x219)
|
|
uint32_t reserved_538; // offset: 538 (0x21A)
|
|
uint32_t reserved_539; // offset: 539 (0x21B)
|
|
uint32_t reserved_540; // offset: 540 (0x21C)
|
|
uint32_t reserved_541; // offset: 541 (0x21D)
|
|
uint32_t reserved_542; // offset: 542 (0x21E)
|
|
uint32_t reserved_543; // offset: 543 (0x21F)
|
|
uint32_t reserved_544; // offset: 544 (0x220)
|
|
uint32_t reserved_545; // offset: 545 (0x221)
|
|
uint32_t reserved_546; // offset: 546 (0x222)
|
|
uint32_t reserved_547; // offset: 547 (0x223)
|
|
uint32_t reserved_548; // offset: 548 (0x224)
|
|
uint32_t reserved_549; // offset: 549 (0x225)
|
|
uint32_t reserved_550; // offset: 550 (0x226)
|
|
uint32_t reserved_551; // offset: 551 (0x227)
|
|
uint32_t reserved_552; // offset: 552 (0x228)
|
|
uint32_t reserved_553; // offset: 553 (0x229)
|
|
uint32_t reserved_554; // offset: 554 (0x22A)
|
|
uint32_t reserved_555; // offset: 555 (0x22B)
|
|
uint32_t reserved_556; // offset: 556 (0x22C)
|
|
uint32_t reserved_557; // offset: 557 (0x22D)
|
|
uint32_t reserved_558; // offset: 558 (0x22E)
|
|
uint32_t reserved_559; // offset: 559 (0x22F)
|
|
uint32_t reserved_560; // offset: 560 (0x230)
|
|
uint32_t reserved_561; // offset: 561 (0x231)
|
|
uint32_t reserved_562; // offset: 562 (0x232)
|
|
uint32_t reserved_563; // offset: 563 (0x233)
|
|
uint32_t reserved_564; // offset: 564 (0x234)
|
|
uint32_t reserved_565; // offset: 565 (0x235)
|
|
uint32_t reserved_566; // offset: 566 (0x236)
|
|
uint32_t reserved_567; // offset: 567 (0x237)
|
|
uint32_t reserved_568; // offset: 568 (0x238)
|
|
uint32_t reserved_569; // offset: 569 (0x239)
|
|
uint32_t reserved_570; // offset: 570 (0x23A)
|
|
uint32_t reserved_571; // offset: 571 (0x23B)
|
|
uint32_t reserved_572; // offset: 572 (0x23C)
|
|
uint32_t reserved_573; // offset: 573 (0x23D)
|
|
uint32_t reserved_574; // offset: 574 (0x23E)
|
|
uint32_t reserved_575; // offset: 575 (0x23F)
|
|
uint32_t reserved_576; // offset: 576 (0x240)
|
|
uint32_t reserved_577; // offset: 577 (0x241)
|
|
uint32_t reserved_578; // offset: 578 (0x242)
|
|
uint32_t reserved_579; // offset: 579 (0x243)
|
|
uint32_t reserved_580; // offset: 580 (0x244)
|
|
uint32_t reserved_581; // offset: 581 (0x245)
|
|
uint32_t reserved_582; // offset: 582 (0x246)
|
|
uint32_t reserved_583; // offset: 583 (0x247)
|
|
uint32_t reserved_584; // offset: 584 (0x248)
|
|
uint32_t reserved_585; // offset: 585 (0x249)
|
|
uint32_t reserved_586; // offset: 586 (0x24A)
|
|
uint32_t reserved_587; // offset: 587 (0x24B)
|
|
uint32_t reserved_588; // offset: 588 (0x24C)
|
|
uint32_t reserved_589; // offset: 589 (0x24D)
|
|
uint32_t reserved_590; // offset: 590 (0x24E)
|
|
uint32_t reserved_591; // offset: 591 (0x24F)
|
|
uint32_t reserved_592; // offset: 592 (0x250)
|
|
uint32_t reserved_593; // offset: 593 (0x251)
|
|
uint32_t reserved_594; // offset: 594 (0x252)
|
|
uint32_t reserved_595; // offset: 595 (0x253)
|
|
uint32_t reserved_596; // offset: 596 (0x254)
|
|
uint32_t reserved_597; // offset: 597 (0x255)
|
|
uint32_t reserved_598; // offset: 598 (0x256)
|
|
uint32_t reserved_599; // offset: 599 (0x257)
|
|
uint32_t reserved_600; // offset: 600 (0x258)
|
|
uint32_t reserved_601; // offset: 601 (0x259)
|
|
uint32_t reserved_602; // offset: 602 (0x25A)
|
|
uint32_t reserved_603; // offset: 603 (0x25B)
|
|
uint32_t reserved_604; // offset: 604 (0x25C)
|
|
uint32_t reserved_605; // offset: 605 (0x25D)
|
|
uint32_t reserved_606; // offset: 606 (0x25E)
|
|
uint32_t reserved_607; // offset: 607 (0x25F)
|
|
uint32_t reserved_608; // offset: 608 (0x260)
|
|
uint32_t reserved_609; // offset: 609 (0x261)
|
|
uint32_t reserved_610; // offset: 610 (0x262)
|
|
uint32_t reserved_611; // offset: 611 (0x263)
|
|
uint32_t reserved_612; // offset: 612 (0x264)
|
|
uint32_t reserved_613; // offset: 613 (0x265)
|
|
uint32_t reserved_614; // offset: 614 (0x266)
|
|
uint32_t reserved_615; // offset: 615 (0x267)
|
|
uint32_t reserved_616; // offset: 616 (0x268)
|
|
uint32_t reserved_617; // offset: 617 (0x269)
|
|
uint32_t reserved_618; // offset: 618 (0x26A)
|
|
uint32_t reserved_619; // offset: 619 (0x26B)
|
|
uint32_t reserved_620; // offset: 620 (0x26C)
|
|
uint32_t reserved_621; // offset: 621 (0x26D)
|
|
uint32_t reserved_622; // offset: 622 (0x26E)
|
|
uint32_t reserved_623; // offset: 623 (0x26F)
|
|
uint32_t reserved_624; // offset: 624 (0x270)
|
|
uint32_t reserved_625; // offset: 625 (0x271)
|
|
uint32_t reserved_626; // offset: 626 (0x272)
|
|
uint32_t reserved_627; // offset: 627 (0x273)
|
|
uint32_t reserved_628; // offset: 628 (0x274)
|
|
uint32_t reserved_629; // offset: 629 (0x275)
|
|
uint32_t reserved_630; // offset: 630 (0x276)
|
|
uint32_t reserved_631; // offset: 631 (0x277)
|
|
uint32_t reserved_632; // offset: 632 (0x278)
|
|
uint32_t reserved_633; // offset: 633 (0x279)
|
|
uint32_t reserved_634; // offset: 634 (0x27A)
|
|
uint32_t reserved_635; // offset: 635 (0x27B)
|
|
uint32_t reserved_636; // offset: 636 (0x27C)
|
|
uint32_t reserved_637; // offset: 637 (0x27D)
|
|
uint32_t reserved_638; // offset: 638 (0x27E)
|
|
uint32_t reserved_639; // offset: 639 (0x27F)
|
|
uint32_t reserved_640; // offset: 640 (0x280)
|
|
uint32_t reserved_641; // offset: 641 (0x281)
|
|
uint32_t reserved_642; // offset: 642 (0x282)
|
|
uint32_t reserved_643; // offset: 643 (0x283)
|
|
uint32_t reserved_644; // offset: 644 (0x284)
|
|
uint32_t reserved_645; // offset: 645 (0x285)
|
|
uint32_t reserved_646; // offset: 646 (0x286)
|
|
uint32_t reserved_647; // offset: 647 (0x287)
|
|
uint32_t reserved_648; // offset: 648 (0x288)
|
|
uint32_t reserved_649; // offset: 649 (0x289)
|
|
uint32_t reserved_650; // offset: 650 (0x28A)
|
|
uint32_t reserved_651; // offset: 651 (0x28B)
|
|
uint32_t reserved_652; // offset: 652 (0x28C)
|
|
uint32_t reserved_653; // offset: 653 (0x28D)
|
|
uint32_t reserved_654; // offset: 654 (0x28E)
|
|
uint32_t reserved_655; // offset: 655 (0x28F)
|
|
uint32_t reserved_656; // offset: 656 (0x290)
|
|
uint32_t reserved_657; // offset: 657 (0x291)
|
|
uint32_t reserved_658; // offset: 658 (0x292)
|
|
uint32_t reserved_659; // offset: 659 (0x293)
|
|
uint32_t reserved_660; // offset: 660 (0x294)
|
|
uint32_t reserved_661; // offset: 661 (0x295)
|
|
uint32_t reserved_662; // offset: 662 (0x296)
|
|
uint32_t reserved_663; // offset: 663 (0x297)
|
|
uint32_t reserved_664; // offset: 664 (0x298)
|
|
uint32_t reserved_665; // offset: 665 (0x299)
|
|
uint32_t reserved_666; // offset: 666 (0x29A)
|
|
uint32_t reserved_667; // offset: 667 (0x29B)
|
|
uint32_t reserved_668; // offset: 668 (0x29C)
|
|
uint32_t reserved_669; // offset: 669 (0x29D)
|
|
uint32_t reserved_670; // offset: 670 (0x29E)
|
|
uint32_t reserved_671; // offset: 671 (0x29F)
|
|
uint32_t reserved_672; // offset: 672 (0x2A0)
|
|
uint32_t reserved_673; // offset: 673 (0x2A1)
|
|
uint32_t reserved_674; // offset: 674 (0x2A2)
|
|
uint32_t reserved_675; // offset: 675 (0x2A3)
|
|
uint32_t reserved_676; // offset: 676 (0x2A4)
|
|
uint32_t reserved_677; // offset: 677 (0x2A5)
|
|
uint32_t reserved_678; // offset: 678 (0x2A6)
|
|
uint32_t reserved_679; // offset: 679 (0x2A7)
|
|
uint32_t reserved_680; // offset: 680 (0x2A8)
|
|
uint32_t reserved_681; // offset: 681 (0x2A9)
|
|
uint32_t reserved_682; // offset: 682 (0x2AA)
|
|
uint32_t reserved_683; // offset: 683 (0x2AB)
|
|
uint32_t reserved_684; // offset: 684 (0x2AC)
|
|
uint32_t reserved_685; // offset: 685 (0x2AD)
|
|
uint32_t reserved_686; // offset: 686 (0x2AE)
|
|
uint32_t reserved_687; // offset: 687 (0x2AF)
|
|
uint32_t reserved_688; // offset: 688 (0x2B0)
|
|
uint32_t reserved_689; // offset: 689 (0x2B1)
|
|
uint32_t reserved_690; // offset: 690 (0x2B2)
|
|
uint32_t reserved_691; // offset: 691 (0x2B3)
|
|
uint32_t reserved_692; // offset: 692 (0x2B4)
|
|
uint32_t reserved_693; // offset: 693 (0x2B5)
|
|
uint32_t reserved_694; // offset: 694 (0x2B6)
|
|
uint32_t reserved_695; // offset: 695 (0x2B7)
|
|
uint32_t reserved_696; // offset: 696 (0x2B8)
|
|
uint32_t reserved_697; // offset: 697 (0x2B9)
|
|
uint32_t reserved_698; // offset: 698 (0x2BA)
|
|
uint32_t reserved_699; // offset: 699 (0x2BB)
|
|
uint32_t reserved_700; // offset: 700 (0x2BC)
|
|
uint32_t reserved_701; // offset: 701 (0x2BD)
|
|
uint32_t reserved_702; // offset: 702 (0x2BE)
|
|
uint32_t reserved_703; // offset: 703 (0x2BF)
|
|
uint32_t reserved_704; // offset: 704 (0x2C0)
|
|
uint32_t reserved_705; // offset: 705 (0x2C1)
|
|
uint32_t reserved_706; // offset: 706 (0x2C2)
|
|
uint32_t reserved_707; // offset: 707 (0x2C3)
|
|
uint32_t reserved_708; // offset: 708 (0x2C4)
|
|
uint32_t reserved_709; // offset: 709 (0x2C5)
|
|
uint32_t reserved_710; // offset: 710 (0x2C6)
|
|
uint32_t reserved_711; // offset: 711 (0x2C7)
|
|
uint32_t reserved_712; // offset: 712 (0x2C8)
|
|
uint32_t reserved_713; // offset: 713 (0x2C9)
|
|
uint32_t reserved_714; // offset: 714 (0x2CA)
|
|
uint32_t reserved_715; // offset: 715 (0x2CB)
|
|
uint32_t reserved_716; // offset: 716 (0x2CC)
|
|
uint32_t reserved_717; // offset: 717 (0x2CD)
|
|
uint32_t reserved_718; // offset: 718 (0x2CE)
|
|
uint32_t reserved_719; // offset: 719 (0x2CF)
|
|
uint32_t reserved_720; // offset: 720 (0x2D0)
|
|
uint32_t reserved_721; // offset: 721 (0x2D1)
|
|
uint32_t reserved_722; // offset: 722 (0x2D2)
|
|
uint32_t reserved_723; // offset: 723 (0x2D3)
|
|
uint32_t reserved_724; // offset: 724 (0x2D4)
|
|
uint32_t reserved_725; // offset: 725 (0x2D5)
|
|
uint32_t reserved_726; // offset: 726 (0x2D6)
|
|
uint32_t reserved_727; // offset: 727 (0x2D7)
|
|
uint32_t reserved_728; // offset: 728 (0x2D8)
|
|
uint32_t reserved_729; // offset: 729 (0x2D9)
|
|
uint32_t reserved_730; // offset: 730 (0x2DA)
|
|
uint32_t reserved_731; // offset: 731 (0x2DB)
|
|
uint32_t reserved_732; // offset: 732 (0x2DC)
|
|
uint32_t reserved_733; // offset: 733 (0x2DD)
|
|
uint32_t reserved_734; // offset: 734 (0x2DE)
|
|
uint32_t reserved_735; // offset: 735 (0x2DF)
|
|
uint32_t reserved_736; // offset: 736 (0x2E0)
|
|
uint32_t reserved_737; // offset: 737 (0x2E1)
|
|
uint32_t reserved_738; // offset: 738 (0x2E2)
|
|
uint32_t reserved_739; // offset: 739 (0x2E3)
|
|
uint32_t reserved_740; // offset: 740 (0x2E4)
|
|
uint32_t reserved_741; // offset: 741 (0x2E5)
|
|
uint32_t reserved_742; // offset: 742 (0x2E6)
|
|
uint32_t reserved_743; // offset: 743 (0x2E7)
|
|
uint32_t reserved_744; // offset: 744 (0x2E8)
|
|
uint32_t reserved_745; // offset: 745 (0x2E9)
|
|
uint32_t reserved_746; // offset: 746 (0x2EA)
|
|
uint32_t reserved_747; // offset: 747 (0x2EB)
|
|
uint32_t reserved_748; // offset: 748 (0x2EC)
|
|
uint32_t reserved_749; // offset: 749 (0x2ED)
|
|
uint32_t reserved_750; // offset: 750 (0x2EE)
|
|
uint32_t reserved_751; // offset: 751 (0x2EF)
|
|
uint32_t reserved_752; // offset: 752 (0x2F0)
|
|
uint32_t reserved_753; // offset: 753 (0x2F1)
|
|
uint32_t reserved_754; // offset: 754 (0x2F2)
|
|
uint32_t reserved_755; // offset: 755 (0x2F3)
|
|
uint32_t reserved_756; // offset: 756 (0x2F4)
|
|
uint32_t reserved_757; // offset: 757 (0x2F5)
|
|
uint32_t reserved_758; // offset: 758 (0x2F6)
|
|
uint32_t reserved_759; // offset: 759 (0x2F7)
|
|
uint32_t reserved_760; // offset: 760 (0x2F8)
|
|
uint32_t reserved_761; // offset: 761 (0x2F9)
|
|
uint32_t reserved_762; // offset: 762 (0x2FA)
|
|
uint32_t reserved_763; // offset: 763 (0x2FB)
|
|
uint32_t reserved_764; // offset: 764 (0x2FC)
|
|
uint32_t reserved_765; // offset: 765 (0x2FD)
|
|
uint32_t reserved_766; // offset: 766 (0x2FE)
|
|
uint32_t reserved_767; // offset: 767 (0x2FF)
|
|
uint32_t reserved_768; // offset: 768 (0x300)
|
|
uint32_t reserved_769; // offset: 769 (0x301)
|
|
uint32_t reserved_770; // offset: 770 (0x302)
|
|
uint32_t reserved_771; // offset: 771 (0x303)
|
|
uint32_t reserved_772; // offset: 772 (0x304)
|
|
uint32_t reserved_773; // offset: 773 (0x305)
|
|
uint32_t reserved_774; // offset: 774 (0x306)
|
|
uint32_t reserved_775; // offset: 775 (0x307)
|
|
uint32_t reserved_776; // offset: 776 (0x308)
|
|
uint32_t reserved_777; // offset: 777 (0x309)
|
|
uint32_t reserved_778; // offset: 778 (0x30A)
|
|
uint32_t reserved_779; // offset: 779 (0x30B)
|
|
uint32_t reserved_780; // offset: 780 (0x30C)
|
|
uint32_t reserved_781; // offset: 781 (0x30D)
|
|
uint32_t reserved_782; // offset: 782 (0x30E)
|
|
uint32_t reserved_783; // offset: 783 (0x30F)
|
|
uint32_t reserved_784; // offset: 784 (0x310)
|
|
uint32_t reserved_785; // offset: 785 (0x311)
|
|
uint32_t reserved_786; // offset: 786 (0x312)
|
|
uint32_t reserved_787; // offset: 787 (0x313)
|
|
uint32_t reserved_788; // offset: 788 (0x314)
|
|
uint32_t reserved_789; // offset: 789 (0x315)
|
|
uint32_t reserved_790; // offset: 790 (0x316)
|
|
uint32_t reserved_791; // offset: 791 (0x317)
|
|
uint32_t reserved_792; // offset: 792 (0x318)
|
|
uint32_t reserved_793; // offset: 793 (0x319)
|
|
uint32_t reserved_794; // offset: 794 (0x31A)
|
|
uint32_t reserved_795; // offset: 795 (0x31B)
|
|
uint32_t reserved_796; // offset: 796 (0x31C)
|
|
uint32_t reserved_797; // offset: 797 (0x31D)
|
|
uint32_t reserved_798; // offset: 798 (0x31E)
|
|
uint32_t reserved_799; // offset: 799 (0x31F)
|
|
uint32_t reserved_800; // offset: 800 (0x320)
|
|
uint32_t reserved_801; // offset: 801 (0x321)
|
|
uint32_t reserved_802; // offset: 802 (0x322)
|
|
uint32_t reserved_803; // offset: 803 (0x323)
|
|
uint32_t reserved_804; // offset: 804 (0x324)
|
|
uint32_t reserved_805; // offset: 805 (0x325)
|
|
uint32_t reserved_806; // offset: 806 (0x326)
|
|
uint32_t reserved_807; // offset: 807 (0x327)
|
|
uint32_t reserved_808; // offset: 808 (0x328)
|
|
uint32_t reserved_809; // offset: 809 (0x329)
|
|
uint32_t reserved_810; // offset: 810 (0x32A)
|
|
uint32_t reserved_811; // offset: 811 (0x32B)
|
|
uint32_t reserved_812; // offset: 812 (0x32C)
|
|
uint32_t reserved_813; // offset: 813 (0x32D)
|
|
uint32_t reserved_814; // offset: 814 (0x32E)
|
|
uint32_t reserved_815; // offset: 815 (0x32F)
|
|
uint32_t reserved_816; // offset: 816 (0x330)
|
|
uint32_t reserved_817; // offset: 817 (0x331)
|
|
uint32_t reserved_818; // offset: 818 (0x332)
|
|
uint32_t reserved_819; // offset: 819 (0x333)
|
|
uint32_t reserved_820; // offset: 820 (0x334)
|
|
uint32_t reserved_821; // offset: 821 (0x335)
|
|
uint32_t reserved_822; // offset: 822 (0x336)
|
|
uint32_t reserved_823; // offset: 823 (0x337)
|
|
uint32_t reserved_824; // offset: 824 (0x338)
|
|
uint32_t reserved_825; // offset: 825 (0x339)
|
|
uint32_t reserved_826; // offset: 826 (0x33A)
|
|
uint32_t reserved_827; // offset: 827 (0x33B)
|
|
uint32_t reserved_828; // offset: 828 (0x33C)
|
|
uint32_t reserved_829; // offset: 829 (0x33D)
|
|
uint32_t reserved_830; // offset: 830 (0x33E)
|
|
uint32_t reserved_831; // offset: 831 (0x33F)
|
|
uint32_t reserved_832; // offset: 832 (0x340)
|
|
uint32_t reserved_833; // offset: 833 (0x341)
|
|
uint32_t reserved_834; // offset: 834 (0x342)
|
|
uint32_t reserved_835; // offset: 835 (0x343)
|
|
uint32_t reserved_836; // offset: 836 (0x344)
|
|
uint32_t reserved_837; // offset: 837 (0x345)
|
|
uint32_t reserved_838; // offset: 838 (0x346)
|
|
uint32_t reserved_839; // offset: 839 (0x347)
|
|
uint32_t reserved_840; // offset: 840 (0x348)
|
|
uint32_t reserved_841; // offset: 841 (0x349)
|
|
uint32_t reserved_842; // offset: 842 (0x34A)
|
|
uint32_t reserved_843; // offset: 843 (0x34B)
|
|
uint32_t reserved_844; // offset: 844 (0x34C)
|
|
uint32_t reserved_845; // offset: 845 (0x34D)
|
|
uint32_t reserved_846; // offset: 846 (0x34E)
|
|
uint32_t reserved_847; // offset: 847 (0x34F)
|
|
uint32_t reserved_848; // offset: 848 (0x350)
|
|
uint32_t reserved_849; // offset: 849 (0x351)
|
|
uint32_t reserved_850; // offset: 850 (0x352)
|
|
uint32_t reserved_851; // offset: 851 (0x353)
|
|
uint32_t reserved_852; // offset: 852 (0x354)
|
|
uint32_t reserved_853; // offset: 853 (0x355)
|
|
uint32_t reserved_854; // offset: 854 (0x356)
|
|
uint32_t reserved_855; // offset: 855 (0x357)
|
|
uint32_t reserved_856; // offset: 856 (0x358)
|
|
uint32_t reserved_857; // offset: 857 (0x359)
|
|
uint32_t reserved_858; // offset: 858 (0x35A)
|
|
uint32_t reserved_859; // offset: 859 (0x35B)
|
|
uint32_t reserved_860; // offset: 860 (0x35C)
|
|
uint32_t reserved_861; // offset: 861 (0x35D)
|
|
uint32_t reserved_862; // offset: 862 (0x35E)
|
|
uint32_t reserved_863; // offset: 863 (0x35F)
|
|
uint32_t reserved_864; // offset: 864 (0x360)
|
|
uint32_t reserved_865; // offset: 865 (0x361)
|
|
uint32_t reserved_866; // offset: 866 (0x362)
|
|
uint32_t reserved_867; // offset: 867 (0x363)
|
|
uint32_t reserved_868; // offset: 868 (0x364)
|
|
uint32_t reserved_869; // offset: 869 (0x365)
|
|
uint32_t reserved_870; // offset: 870 (0x366)
|
|
uint32_t reserved_871; // offset: 871 (0x367)
|
|
uint32_t reserved_872; // offset: 872 (0x368)
|
|
uint32_t reserved_873; // offset: 873 (0x369)
|
|
uint32_t reserved_874; // offset: 874 (0x36A)
|
|
uint32_t reserved_875; // offset: 875 (0x36B)
|
|
uint32_t reserved_876; // offset: 876 (0x36C)
|
|
uint32_t reserved_877; // offset: 877 (0x36D)
|
|
uint32_t reserved_878; // offset: 878 (0x36E)
|
|
uint32_t reserved_879; // offset: 879 (0x36F)
|
|
uint32_t reserved_880; // offset: 880 (0x370)
|
|
uint32_t reserved_881; // offset: 881 (0x371)
|
|
uint32_t reserved_882; // offset: 882 (0x372)
|
|
uint32_t reserved_883; // offset: 883 (0x373)
|
|
uint32_t reserved_884; // offset: 884 (0x374)
|
|
uint32_t reserved_885; // offset: 885 (0x375)
|
|
uint32_t reserved_886; // offset: 886 (0x376)
|
|
uint32_t reserved_887; // offset: 887 (0x377)
|
|
uint32_t reserved_888; // offset: 888 (0x378)
|
|
uint32_t reserved_889; // offset: 889 (0x379)
|
|
uint32_t reserved_890; // offset: 890 (0x37A)
|
|
uint32_t reserved_891; // offset: 891 (0x37B)
|
|
uint32_t reserved_892; // offset: 892 (0x37C)
|
|
uint32_t reserved_893; // offset: 893 (0x37D)
|
|
uint32_t reserved_894; // offset: 894 (0x37E)
|
|
uint32_t reserved_895; // offset: 895 (0x37F)
|
|
uint32_t reserved_896; // offset: 896 (0x380)
|
|
uint32_t reserved_897; // offset: 897 (0x381)
|
|
uint32_t reserved_898; // offset: 898 (0x382)
|
|
uint32_t reserved_899; // offset: 899 (0x383)
|
|
uint32_t reserved_900; // offset: 900 (0x384)
|
|
uint32_t reserved_901; // offset: 901 (0x385)
|
|
uint32_t reserved_902; // offset: 902 (0x386)
|
|
uint32_t reserved_903; // offset: 903 (0x387)
|
|
uint32_t reserved_904; // offset: 904 (0x388)
|
|
uint32_t reserved_905; // offset: 905 (0x389)
|
|
uint32_t reserved_906; // offset: 906 (0x38A)
|
|
uint32_t reserved_907; // offset: 907 (0x38B)
|
|
uint32_t reserved_908; // offset: 908 (0x38C)
|
|
uint32_t reserved_909; // offset: 909 (0x38D)
|
|
uint32_t reserved_910; // offset: 910 (0x38E)
|
|
uint32_t reserved_911; // offset: 911 (0x38F)
|
|
uint32_t reserved_912; // offset: 912 (0x390)
|
|
uint32_t reserved_913; // offset: 913 (0x391)
|
|
uint32_t reserved_914; // offset: 914 (0x392)
|
|
uint32_t reserved_915; // offset: 915 (0x393)
|
|
uint32_t reserved_916; // offset: 916 (0x394)
|
|
uint32_t reserved_917; // offset: 917 (0x395)
|
|
uint32_t reserved_918; // offset: 918 (0x396)
|
|
uint32_t reserved_919; // offset: 919 (0x397)
|
|
uint32_t reserved_920; // offset: 920 (0x398)
|
|
uint32_t reserved_921; // offset: 921 (0x399)
|
|
uint32_t reserved_922; // offset: 922 (0x39A)
|
|
uint32_t reserved_923; // offset: 923 (0x39B)
|
|
uint32_t reserved_924; // offset: 924 (0x39C)
|
|
uint32_t reserved_925; // offset: 925 (0x39D)
|
|
uint32_t reserved_926; // offset: 926 (0x39E)
|
|
uint32_t reserved_927; // offset: 927 (0x39F)
|
|
uint32_t reserved_928; // offset: 928 (0x3A0)
|
|
uint32_t reserved_929; // offset: 929 (0x3A1)
|
|
uint32_t reserved_930; // offset: 930 (0x3A2)
|
|
uint32_t reserved_931; // offset: 931 (0x3A3)
|
|
uint32_t reserved_932; // offset: 932 (0x3A4)
|
|
uint32_t reserved_933; // offset: 933 (0x3A5)
|
|
uint32_t reserved_934; // offset: 934 (0x3A6)
|
|
uint32_t reserved_935; // offset: 935 (0x3A7)
|
|
uint32_t reserved_936; // offset: 936 (0x3A8)
|
|
uint32_t reserved_937; // offset: 937 (0x3A9)
|
|
uint32_t reserved_938; // offset: 938 (0x3AA)
|
|
uint32_t reserved_939; // offset: 939 (0x3AB)
|
|
uint32_t reserved_940; // offset: 940 (0x3AC)
|
|
uint32_t reserved_941; // offset: 941 (0x3AD)
|
|
uint32_t reserved_942; // offset: 942 (0x3AE)
|
|
uint32_t reserved_943; // offset: 943 (0x3AF)
|
|
uint32_t reserved_944; // offset: 944 (0x3B0)
|
|
uint32_t reserved_945; // offset: 945 (0x3B1)
|
|
uint32_t reserved_946; // offset: 946 (0x3B2)
|
|
uint32_t reserved_947; // offset: 947 (0x3B3)
|
|
uint32_t reserved_948; // offset: 948 (0x3B4)
|
|
uint32_t reserved_949; // offset: 949 (0x3B5)
|
|
uint32_t reserved_950; // offset: 950 (0x3B6)
|
|
uint32_t reserved_951; // offset: 951 (0x3B7)
|
|
uint32_t reserved_952; // offset: 952 (0x3B8)
|
|
uint32_t reserved_953; // offset: 953 (0x3B9)
|
|
uint32_t reserved_954; // offset: 954 (0x3BA)
|
|
uint32_t reserved_955; // offset: 955 (0x3BB)
|
|
uint32_t reserved_956; // offset: 956 (0x3BC)
|
|
uint32_t reserved_957; // offset: 957 (0x3BD)
|
|
uint32_t reserved_958; // offset: 958 (0x3BE)
|
|
uint32_t reserved_959; // offset: 959 (0x3BF)
|
|
uint32_t reserved_960; // offset: 960 (0x3C0)
|
|
uint32_t reserved_961; // offset: 961 (0x3C1)
|
|
uint32_t reserved_962; // offset: 962 (0x3C2)
|
|
uint32_t reserved_963; // offset: 963 (0x3C3)
|
|
uint32_t reserved_964; // offset: 964 (0x3C4)
|
|
uint32_t reserved_965; // offset: 965 (0x3C5)
|
|
uint32_t reserved_966; // offset: 966 (0x3C6)
|
|
uint32_t reserved_967; // offset: 967 (0x3C7)
|
|
uint32_t reserved_968; // offset: 968 (0x3C8)
|
|
uint32_t reserved_969; // offset: 969 (0x3C9)
|
|
uint32_t reserved_970; // offset: 970 (0x3CA)
|
|
uint32_t reserved_971; // offset: 971 (0x3CB)
|
|
uint32_t reserved_972; // offset: 972 (0x3CC)
|
|
uint32_t reserved_973; // offset: 973 (0x3CD)
|
|
uint32_t reserved_974; // offset: 974 (0x3CE)
|
|
uint32_t reserved_975; // offset: 975 (0x3CF)
|
|
uint32_t reserved_976; // offset: 976 (0x3D0)
|
|
uint32_t reserved_977; // offset: 977 (0x3D1)
|
|
uint32_t reserved_978; // offset: 978 (0x3D2)
|
|
uint32_t reserved_979; // offset: 979 (0x3D3)
|
|
uint32_t reserved_980; // offset: 980 (0x3D4)
|
|
uint32_t reserved_981; // offset: 981 (0x3D5)
|
|
uint32_t reserved_982; // offset: 982 (0x3D6)
|
|
uint32_t reserved_983; // offset: 983 (0x3D7)
|
|
uint32_t reserved_984; // offset: 984 (0x3D8)
|
|
uint32_t reserved_985; // offset: 985 (0x3D9)
|
|
uint32_t reserved_986; // offset: 986 (0x3DA)
|
|
uint32_t reserved_987; // offset: 987 (0x3DB)
|
|
uint32_t reserved_988; // offset: 988 (0x3DC)
|
|
uint32_t reserved_989; // offset: 989 (0x3DD)
|
|
uint32_t reserved_990; // offset: 990 (0x3DE)
|
|
uint32_t reserved_991; // offset: 991 (0x3DF)
|
|
uint32_t reserved_992; // offset: 992 (0x3E0)
|
|
uint32_t reserved_993; // offset: 993 (0x3E1)
|
|
uint32_t reserved_994; // offset: 994 (0x3E2)
|
|
uint32_t reserved_995; // offset: 995 (0x3E3)
|
|
uint32_t reserved_996; // offset: 996 (0x3E4)
|
|
uint32_t reserved_997; // offset: 997 (0x3E5)
|
|
uint32_t reserved_998; // offset: 998 (0x3E6)
|
|
uint32_t reserved_999; // offset: 999 (0x3E7)
|
|
uint32_t reserved_1000; // offset: 1000 (0x3E8)
|
|
uint32_t reserved_1001; // offset: 1001 (0x3E9)
|
|
uint32_t reserved_1002; // offset: 1002 (0x3EA)
|
|
uint32_t reserved_1003; // offset: 1003 (0x3EB)
|
|
uint32_t reserved_1004; // offset: 1004 (0x3EC)
|
|
uint32_t reserved_1005; // offset: 1005 (0x3ED)
|
|
uint32_t reserved_1006; // offset: 1006 (0x3EE)
|
|
uint32_t reserved_1007; // offset: 1007 (0x3EF)
|
|
uint32_t reserved_1008; // offset: 1008 (0x3F0)
|
|
uint32_t reserved_1009; // offset: 1009 (0x3F1)
|
|
uint32_t reserved_1010; // offset: 1010 (0x3F2)
|
|
uint32_t reserved_1011; // offset: 1011 (0x3F3)
|
|
uint32_t reserved_1012; // offset: 1012 (0x3F4)
|
|
uint32_t reserved_1013; // offset: 1013 (0x3F5)
|
|
uint32_t reserved_1014; // offset: 1014 (0x3F6)
|
|
uint32_t reserved_1015; // offset: 1015 (0x3F7)
|
|
uint32_t reserved_1016; // offset: 1016 (0x3F8)
|
|
uint32_t reserved_1017; // offset: 1017 (0x3F9)
|
|
uint32_t reserved_1018; // offset: 1018 (0x3FA)
|
|
uint32_t reserved_1019; // offset: 1019 (0x3FB)
|
|
uint32_t reserved_1020; // offset: 1020 (0x3FC)
|
|
uint32_t reserved_1021; // offset: 1021 (0x3FD)
|
|
uint32_t reserved_1022; // offset: 1022 (0x3FE)
|
|
uint32_t reserved_1023; // offset: 1023 (0x3FF)
|
|
};
|
|
|
|
struct v12_1_mes_mqd {
|
|
uint32_t header; // offset: 0 (0x0)
|
|
uint32_t compute_dispatch_initiator; // offset: 1 (0x1)
|
|
uint32_t compute_dim_x; // offset: 2 (0x2)
|
|
uint32_t compute_dim_y; // offset: 3 (0x3)
|
|
uint32_t compute_dim_z; // offset: 4 (0x4)
|
|
uint32_t compute_start_x; // offset: 5 (0x5)
|
|
uint32_t compute_start_y; // offset: 6 (0x6)
|
|
uint32_t compute_start_z; // offset: 7 (0x7)
|
|
uint32_t compute_num_thread_x; // offset: 8 (0x8)
|
|
uint32_t compute_num_thread_y; // offset: 9 (0x9)
|
|
uint32_t compute_num_thread_z; // offset: 10 (0xA)
|
|
uint32_t compute_pipelinestat_enable; // offset: 11 (0xB)
|
|
uint32_t compute_perfcount_enable; // offset: 12 (0xC)
|
|
uint32_t compute_pgm_lo; // offset: 13 (0xD)
|
|
uint32_t compute_pgm_hi; // offset: 14 (0xE)
|
|
uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF)
|
|
uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10)
|
|
uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11)
|
|
uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12)
|
|
uint32_t compute_pgm_rsrc1; // offset: 19 (0x13)
|
|
uint32_t compute_pgm_rsrc2; // offset: 20 (0x14)
|
|
uint32_t compute_vmid; // offset: 21 (0x15)
|
|
uint32_t compute_resource_limits; // offset: 22 (0x16)
|
|
uint32_t compute_tmpring_size; // offset: 23 (0x17)
|
|
uint32_t compute_restart_x; // offset: 24 (0x18)
|
|
uint32_t compute_restart_y; // offset: 25 (0x19)
|
|
uint32_t compute_restart_z; // offset: 26 (0x1A)
|
|
uint32_t compute_thread_trace_enable; // offset: 27 (0x1B)
|
|
uint32_t compute_misc_reserved; // offset: 28 (0x1C)
|
|
uint32_t compute_dispatch_id; // offset: 29 (0x1D)
|
|
uint32_t compute_threadgroup_id; // offset: 30 (0x1E)
|
|
uint32_t compute_req_ctrl; // offset: 31 (0x1F)
|
|
uint32_t compute_user_accum_0; // offset: 32 (0x20)
|
|
uint32_t compute_user_accum_1; // offset: 33 (0x21)
|
|
uint32_t compute_user_accum_2; // offset: 34 (0x22)
|
|
uint32_t compute_user_accum_3; // offset: 35 (0x23)
|
|
uint32_t compute_pgm_rsrc3; // offset: 36 (0x24)
|
|
uint32_t compute_ddid_index; // offset: 37 (0x25)
|
|
uint32_t compute_shader_chksum; // offset: 38 (0x26)
|
|
uint32_t compute_dispatch_interleave; // offset: 39 (0x27)
|
|
uint32_t compute_current_logical_xcc_id; // offset: 40 (0x28)
|
|
uint32_t compute_restart_cg_tg_id; // offset: 41 (0x29)
|
|
uint32_t compute_tg_chunk_size; // offset: 42 (0x2A)
|
|
uint32_t compute_restore_tg_chunk_size; // offset: 43 (0x2B)
|
|
uint32_t compute_start_total_lo; // offset: 44 (0x2C)
|
|
uint32_t compute_start_total_hi; // offset: 45 (0x2D)
|
|
uint32_t compute_prescaled_dim_x; // offset: 46 (0x2E)
|
|
uint32_t compute_prescaled_dim_y; // offset: 47 (0x2F)
|
|
uint32_t compute_prescaled_dim_z; // offset: 48 (0x30)
|
|
uint32_t compute_static_thread_mgmt_se0; // offset: 49 (0x31)
|
|
uint32_t compute_static_thread_mgmt_se1; // offset: 50 (0x32)
|
|
uint32_t compute_static_thread_mgmt_se2; // offset: 51 (0x33)
|
|
uint32_t compute_static_thread_mgmt_se3; // offset: 52 (0x34)
|
|
uint32_t compute_static_thread_mgmt_se4; // offset: 53 (0x35)
|
|
uint32_t compute_static_thread_mgmt_se5; // offset: 54 (0x36)
|
|
uint32_t compute_static_thread_mgmt_se6; // offset: 55 (0x37)
|
|
uint32_t compute_static_thread_mgmt_se7; // offset: 56 (0x38)
|
|
uint32_t compute_static_thread_mgmt_se8; // offset: 57 (0x39)
|
|
uint32_t reserved_58; // offset: 58 (0x3A)
|
|
uint32_t reserved_59; // offset: 59 (0x3B)
|
|
uint32_t reserved_60; // offset: 60 (0x3C)
|
|
uint32_t reserved_61; // offset: 61 (0x3D)
|
|
uint32_t reserved_62; // offset: 62 (0x3E)
|
|
uint32_t reserved_63; // offset: 63 (0x3F)
|
|
uint32_t reserved_64; // offset: 64 (0x40)
|
|
uint32_t compute_user_data_0; // offset: 65 (0x41)
|
|
uint32_t compute_user_data_1; // offset: 66 (0x42)
|
|
uint32_t compute_user_data_2; // offset: 67 (0x43)
|
|
uint32_t compute_user_data_3; // offset: 68 (0x44)
|
|
uint32_t compute_user_data_4; // offset: 69 (0x45)
|
|
uint32_t compute_user_data_5; // offset: 70 (0x46)
|
|
uint32_t compute_user_data_6; // offset: 71 (0x47)
|
|
uint32_t compute_user_data_7; // offset: 72 (0x48)
|
|
uint32_t compute_user_data_8; // offset: 73 (0x49)
|
|
uint32_t compute_user_data_9; // offset: 74 (0x4A)
|
|
uint32_t compute_user_data_10; // offset: 75 (0x4B)
|
|
uint32_t compute_user_data_11; // offset: 76 (0x4C)
|
|
uint32_t compute_user_data_12; // offset: 77 (0x4D)
|
|
uint32_t compute_user_data_13; // offset: 78 (0x4E)
|
|
uint32_t compute_user_data_14; // offset: 79 (0x4F)
|
|
uint32_t compute_user_data_15; // offset: 80 (0x50)
|
|
uint32_t compute_user_data_16; // offset: 81 (0x51)
|
|
uint32_t compute_user_data_17; // offset: 82 (0x52)
|
|
uint32_t compute_user_data_18; // offset: 83 (0x53)
|
|
uint32_t compute_user_data_19; // offset: 84 (0x54)
|
|
uint32_t compute_user_data_20; // offset: 85 (0x55)
|
|
uint32_t compute_user_data_21; // offset: 86 (0x56)
|
|
uint32_t compute_user_data_22; // offset: 87 (0x57)
|
|
uint32_t compute_user_data_23; // offset: 88 (0x58)
|
|
uint32_t compute_user_data_24; // offset: 89 (0x59)
|
|
uint32_t compute_user_data_25; // offset: 90 (0x5A)
|
|
uint32_t compute_user_data_26; // offset: 91 (0x5B)
|
|
uint32_t compute_user_data_27; // offset: 92 (0x5C)
|
|
uint32_t compute_user_data_28; // offset: 93 (0x5D)
|
|
uint32_t compute_user_data_29; // offset: 94 (0x5E)
|
|
uint32_t compute_user_data_30; // offset: 95 (0x5F)
|
|
uint32_t compute_user_data_31; // offset: 96 (0x60)
|
|
uint32_t reserved_97; // offset: 97 (0x61)
|
|
uint32_t reserved_98; // offset: 98 (0x62)
|
|
uint32_t reserved_99; // offset: 99 (0x63)
|
|
uint32_t reserved_100; // offset: 100 (0x64)
|
|
uint32_t reserved_101; // offset: 101 (0x65)
|
|
uint32_t reserved_102; // offset: 102 (0x66)
|
|
uint32_t reserved_103; // offset: 103 (0x67)
|
|
uint32_t reserved_104; // offset: 104 (0x68)
|
|
uint32_t reserved_105; // offset: 105 (0x69)
|
|
uint32_t reserved_106; // offset: 106 (0x6A)
|
|
uint32_t reserved_107; // offset: 107 (0x6B)
|
|
uint32_t reserved_108; // offset: 108 (0x6C)
|
|
uint32_t reserved_109; // offset: 109 (0x6D)
|
|
uint32_t compute_relaunch; // offset: 110 (0x6E)
|
|
uint32_t compute_wave_restore_addr_lo; // offset: 111 (0x6F)
|
|
uint32_t compute_wave_restore_addr_hi; // offset: 112 (0x70)
|
|
uint32_t compute_relaunch2; // offset: 113 (0x71)
|
|
uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72)
|
|
uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73)
|
|
uint32_t cp_packet_id_lo; // offset: 116 (0x74)
|
|
uint32_t cp_packet_id_hi; // offset: 117 (0x75)
|
|
uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76)
|
|
uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77)
|
|
uint32_t reserved_120; // offset: 120 (0x78)
|
|
uint32_t reserved_121; // offset: 121 (0x79)
|
|
uint32_t reserved_122; // offset: 122 (0x7A)
|
|
uint32_t reserved_123; // offset: 123 (0x7B)
|
|
uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C)
|
|
uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D)
|
|
uint32_t reserved_126; // offset: 126 (0x7E)
|
|
uint32_t reserved_127; // offset: 127 (0x7F)
|
|
uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80)
|
|
uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)
|
|
uint32_t cp_hqd_active; // offset: 130 (0x82)
|
|
uint32_t cp_hqd_vmid; // offset: 131 (0x83)
|
|
uint32_t cp_hqd_persistent_state; // offset: 132 (0x84)
|
|
uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85)
|
|
uint32_t cp_hqd_queue_priority; // offset: 134 (0x86)
|
|
uint32_t cp_hqd_quantum; // offset: 135 (0x87)
|
|
uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88)
|
|
uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89)
|
|
uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A)
|
|
uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B)
|
|
uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C)
|
|
uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D)
|
|
uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E)
|
|
uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F)
|
|
uint32_t reserved_144; // offset: 144 (0x90)
|
|
uint32_t cp_hqd_pq_control; // offset: 145 (0x91)
|
|
uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92)
|
|
uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93)
|
|
uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94)
|
|
uint32_t cp_hqd_ib_control; // offset: 149 (0x95)
|
|
uint32_t cp_hqd_iq_timer; // offset: 150 (0x96)
|
|
uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97)
|
|
uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98)
|
|
uint32_t cp_hqd_dma_offload; // offset: 153 (0x99)
|
|
uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A)
|
|
uint32_t cp_hqd_msg_type; // offset: 155 (0x9B)
|
|
uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C)
|
|
uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D)
|
|
uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E)
|
|
uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F)
|
|
uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0)
|
|
uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1)
|
|
uint32_t cp_mqd_control; // offset: 162 (0xA2)
|
|
uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3)
|
|
uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4)
|
|
uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5)
|
|
uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6)
|
|
uint32_t cp_hqd_eop_control; // offset: 167 (0xA7)
|
|
uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8)
|
|
uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9)
|
|
uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA)
|
|
uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB)
|
|
uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC)
|
|
uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD)
|
|
uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE)
|
|
uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF)
|
|
uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0)
|
|
uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1)
|
|
uint32_t reserved_178; // offset: 178 (0xB2)
|
|
uint32_t cp_hqd_error; // offset: 179 (0xB3)
|
|
uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4)
|
|
uint32_t cp_hqd_aql_control; // offset: 181 (0xB5)
|
|
uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6)
|
|
uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7)
|
|
uint32_t cp_hqd_gfx_control; // offset: 184 (0xB8)
|
|
uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; // offset: 185 (0xB9)
|
|
uint32_t cp_hqd_suspend_wg_state_offset; // offset: 186 (0xBA)
|
|
uint32_t cp_hqd_ddid_rptr; // offset: 187 (0xBB)
|
|
uint32_t cp_hqd_ddid_wptr; // offset: 188 (0xBC)
|
|
uint32_t cp_hqd_ddid_inflight_count; // offset: 189 (0xBD)
|
|
uint32_t cp_hqd_ddid_delta_rpt_count; // offset: 190 (0xBE)
|
|
uint32_t cp_hqd_dequeue_status; // offset: 191 (0xBF)
|
|
uint32_t cp_hqd_aql_control_1; // offset: 192 (0xC0)
|
|
uint32_t cp_hqd_aql_dispatch_id; // offset: 193 (0xC1)
|
|
uint32_t cp_hqd_aql_dispatch_id_hi; // offset: 194 (0xC2)
|
|
uint32_t cp_hqd_kd_base; // offset: 195 (0xC3)
|
|
uint32_t cp_hqd_kd_base_hi; // offset: 196 (0xC4)
|
|
uint32_t cp_hqd_kd_cntl; // offset: 197 (0xC5)
|
|
uint32_t reserved_198; // offset: 198 (0xC6)
|
|
uint32_t reserved_199; // offset: 199 (0xC7)
|
|
uint32_t reserved_200; // offset: 200 (0xC8)
|
|
uint32_t reserved_201; // offset: 201 (0xC9)
|
|
uint32_t reserved_202; // offset: 202 (0xCA)
|
|
uint32_t reserved_203; // offset: 203 (0xCB)
|
|
uint32_t reserved_204; // offset: 204 (0xCC)
|
|
uint32_t reserved_205; // offset: 205 (0xCD)
|
|
uint32_t reserved_206; // offset: 206 (0xCE)
|
|
uint32_t reserved_207; // offset: 207 (0xCF)
|
|
uint32_t reserved_208; // offset: 208 (0xD0)
|
|
uint32_t reserved_209; // offset: 209 (0xD1)
|
|
uint32_t reserved_210; // offset: 210 (0xD2)
|
|
uint32_t reserved_211; // offset: 211 (0xD3)
|
|
uint32_t reserved_212; // offset: 212 (0xD4)
|
|
uint32_t reserved_213; // offset: 213 (0xD5)
|
|
uint32_t reserved_214; // offset: 214 (0xD6)
|
|
uint32_t reserved_215; // offset: 215 (0xD7)
|
|
uint32_t reserved_216; // offset: 216 (0xD8)
|
|
uint32_t reserved_217; // offset: 217 (0xD9)
|
|
uint32_t reserved_218; // offset: 218 (0xDA)
|
|
uint32_t reserved_219; // offset: 219 (0xDB)
|
|
uint32_t reserved_220; // offset: 220 (0xDC)
|
|
uint32_t reserved_221; // offset: 221 (0xDD)
|
|
uint32_t reserved_222; // offset: 222 (0xDE)
|
|
uint32_t reserved_223; // offset: 223 (0xDF)
|
|
uint32_t reserved_224; // offset: 224 (0xE0)
|
|
uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1)
|
|
uint32_t cp_mqd_stride_size; // offset: 226 (0xE2)
|
|
uint32_t xcc_sync_counter; // offset: 227 (0xE3)
|
|
uint32_t set_resources_header; // offset: 228 (0xE4)
|
|
uint32_t set_resources_dw1; // offset: 229 (0xE5)
|
|
uint32_t set_resources_dw2; // offset: 230 (0xE6)
|
|
uint32_t set_resources_dw3; // offset: 231 (0xE7)
|
|
uint32_t set_resources_dw4; // offset: 232 (0xE8)
|
|
uint32_t set_resources_dw5; // offset: 233 (0xE9)
|
|
uint32_t set_resources_dw6; // offset: 234 (0xEA)
|
|
uint32_t set_resources_dw7; // offset: 235 (0xEB)
|
|
uint32_t reserved_236; // offset: 236 (0xEC)
|
|
uint32_t reserved_237; // offset: 237 (0xED)
|
|
uint32_t reserved_238; // offset: 238 (0xEE)
|
|
uint32_t reserved_239; // offset: 239 (0xEF)
|
|
uint32_t reserved_240; // offset: 240 (0xF0)
|
|
uint32_t reserved_241; // offset: 241 (0xF1)
|
|
uint32_t reserved_242; // offset: 242 (0xF2)
|
|
uint32_t reserved_243; // offset: 243 (0xF3)
|
|
uint32_t reserved_244; // offset: 244 (0xF4)
|
|
uint32_t reserved_245; // offset: 245 (0xF5)
|
|
uint32_t reserved_246; // offset: 246 (0xF6)
|
|
uint32_t reserved_247; // offset: 247 (0xF7)
|
|
uint32_t reserved_248; // offset: 248 (0xF8)
|
|
uint32_t reserved_249; // offset: 249 (0xF9)
|
|
uint32_t reserved_250; // offset: 250 (0xFA)
|
|
uint32_t reserved_251; // offset: 251 (0xFB)
|
|
uint32_t reserved_252; // offset: 252 (0xFC)
|
|
uint32_t reserved_253; // offset: 253 (0xFD)
|
|
uint32_t reserved_254; // offset: 254 (0xFE)
|
|
uint32_t reserved_255; // offset: 255 (0xFF)
|
|
uint32_t control_buf_addr_lo; // offset: 256 (0x100)
|
|
uint32_t control_buf_addr_hi; // offset: 257 (0x101)
|
|
uint32_t control_buf_wptr_lo; // offset: 258 (0x102)
|
|
uint32_t control_buf_wptr_hi; // offset: 259 (0x103)
|
|
uint32_t control_buf_dptr_lo; // offset: 260 (0x104)
|
|
uint32_t control_buf_dptr_hi; // offset: 261 (0x105)
|
|
uint32_t draw_ring_addr_lo; // offset: 262 (0x106)
|
|
uint32_t draw_ring_addr_hi; // offset: 263 (0x107)
|
|
uint32_t control_buf_num_entries; // offset: 264 (0x108)
|
|
uint32_t reserved_265; // offset: 265 (0x109)
|
|
uint32_t reserved_266; // offset: 266 (0x10A)
|
|
uint32_t reserved_267; // offset: 267 (0x10B)
|
|
uint32_t reserved_268; // offset: 268 (0x10C)
|
|
uint32_t reserved_269; // offset: 269 (0x10D)
|
|
uint32_t reserved_270; // offset: 270 (0x10E)
|
|
uint32_t reserved_271; // offset: 271 (0x10F)
|
|
uint32_t dfwx_flags; // offset: 272 (0x110)
|
|
uint32_t dfwx_slot; // offset: 273 (0x111)
|
|
uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112)
|
|
uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113)
|
|
uint32_t dfwx_queue_connect_addr_lo; // offset: 276 (0x114)
|
|
uint32_t dfwx_queue_connect_addr_hi; // offset: 277 (0x115)
|
|
uint32_t reserved_278; // offset: 278 (0x116)
|
|
uint32_t reserved_279; // offset: 279 (0x117)
|
|
uint32_t reserved_280; // offset: 280 (0x118)
|
|
uint32_t reserved_281; // offset: 281 (0x119)
|
|
uint32_t reserved_282; // offset: 282 (0x11A)
|
|
uint32_t reserved_283; // offset: 283 (0x11B)
|
|
uint32_t reserved_284; // offset: 284 (0x11C)
|
|
uint32_t reserved_285; // offset: 285 (0x11D)
|
|
uint32_t reserved_286; // offset: 286 (0x11E)
|
|
uint32_t reserved_287; // offset: 287 (0x11F)
|
|
uint32_t cp_mqd_query_time_lo; // offset: 288 (0x120)
|
|
uint32_t cp_mqd_query_time_hi; // offset: 289 (0x121)
|
|
uint32_t cp_mqd_connect_start_time_lo; // offset: 290 (0x122)
|
|
uint32_t cp_mqd_connect_start_time_hi; // offset: 291 (0x123)
|
|
uint32_t cp_mqd_connect_end_time_lo; // offset: 292 (0x124)
|
|
uint32_t cp_mqd_connect_end_time_hi; // offset: 293 (0x125)
|
|
uint32_t cp_mqd_connect_end_wf_count; // offset: 294 (0x126)
|
|
uint32_t cp_mqd_connect_end_pq_rptr; // offset: 295 (0x127)
|
|
uint32_t cp_mqd_connect_end_pq_wptr; // offset: 296 (0x128)
|
|
uint32_t cp_mqd_connect_end_ib_rptr; // offset: 297 (0x129)
|
|
uint32_t cp_mqd_readindex_lo; // offset: 298 (0x12A)
|
|
uint32_t cp_mqd_readindex_hi; // offset: 299 (0x12B)
|
|
uint32_t cp_mqd_save_start_time_lo; // offset: 300 (0x12C)
|
|
uint32_t cp_mqd_save_start_time_hi; // offset: 301 (0x12D)
|
|
uint32_t cp_mqd_save_end_time_lo; // offset: 302 (0x12E)
|
|
uint32_t cp_mqd_save_end_time_hi; // offset: 303 (0x12F)
|
|
uint32_t cp_mqd_restore_start_time_lo; // offset: 304 (0x130)
|
|
uint32_t cp_mqd_restore_start_time_hi; // offset: 305 (0x131)
|
|
uint32_t cp_mqd_restore_end_time_lo; // offset: 306 (0x132)
|
|
uint32_t cp_mqd_restore_end_time_hi; // offset: 307 (0x133)
|
|
uint32_t disable_queue; // offset: 308 (0x134)
|
|
uint32_t reserved_309; // offset: 309 (0x135)
|
|
uint32_t reserved_310; // offset: 310 (0x136)
|
|
uint32_t reserved_311; // offset: 311 (0x137)
|
|
uint32_t reserved_312; // offset: 312 (0x138)
|
|
uint32_t reserved_313; // offset: 313 (0x139)
|
|
uint32_t reserved_314; // offset: 314 (0x13A)
|
|
uint32_t reserved_315; // offset: 315 (0x13B)
|
|
uint32_t reserved_316; // offset: 316 (0x13C)
|
|
uint32_t reserved_317; // offset: 317 (0x13D)
|
|
uint32_t tg_counter_id; // offset: 318 (0x13E)
|
|
uint32_t cp_compute_csinvoc_count_lo; // offset: 319 (0x13F)
|
|
uint32_t cp_compute_csinvoc_count_hi; // offset: 320 (0x140)
|
|
uint32_t reserved_321; // offset: 321 (0x141)
|
|
uint32_t reserved_322; // offset: 322 (0x142)
|
|
uint32_t reserved_323; // offset: 323 (0x143)
|
|
uint32_t reserved_324; // offset: 324 (0x144)
|
|
uint32_t reserved_325; // offset: 325 (0x145)
|
|
uint32_t reserved_326; // offset: 326 (0x146)
|
|
uint32_t reserved_327; // offset: 327 (0x147)
|
|
uint32_t reserved_328; // offset: 328 (0x148)
|
|
uint32_t reserved_329; // offset: 329 (0x149)
|
|
uint32_t reserved_330; // offset: 330 (0x14A)
|
|
uint32_t reserved_331; // offset: 331 (0x14B)
|
|
uint32_t reserved_332; // offset: 332 (0x14C)
|
|
uint32_t reserved_333; // offset: 333 (0x14D)
|
|
uint32_t reserved_334; // offset: 334 (0x14E)
|
|
uint32_t reserved_335; // offset: 335 (0x14F)
|
|
uint32_t reserved_336; // offset: 336 (0x150)
|
|
uint32_t reserved_337; // offset: 337 (0x151)
|
|
uint32_t reserved_338; // offset: 338 (0x152)
|
|
uint32_t reserved_339; // offset: 339 (0x153)
|
|
uint32_t reserved_340; // offset: 340 (0x154)
|
|
uint32_t reserved_341; // offset: 341 (0x155)
|
|
uint32_t reserved_342; // offset: 342 (0x156)
|
|
uint32_t reserved_343; // offset: 343 (0x157)
|
|
uint32_t reserved_344; // offset: 344 (0x158)
|
|
uint32_t reserved_345; // offset: 345 (0x159)
|
|
uint32_t reserved_346; // offset: 346 (0x15A)
|
|
uint32_t reserved_347; // offset: 347 (0x15B)
|
|
uint32_t reserved_348; // offset: 348 (0x15C)
|
|
uint32_t reserved_349; // offset: 349 (0x15D)
|
|
uint32_t reserved_350; // offset: 350 (0x15E)
|
|
uint32_t reserved_351; // offset: 351 (0x15F)
|
|
uint32_t reserved_352; // offset: 352 (0x160)
|
|
uint32_t reserved_353; // offset: 353 (0x161)
|
|
uint32_t reserved_354; // offset: 354 (0x162)
|
|
uint32_t reserved_355; // offset: 355 (0x163)
|
|
uint32_t reserved_356; // offset: 356 (0x164)
|
|
uint32_t reserved_357; // offset: 357 (0x165)
|
|
uint32_t reserved_358; // offset: 358 (0x166)
|
|
uint32_t reserved_359; // offset: 359 (0x167)
|
|
uint32_t reserved_360; // offset: 360 (0x168)
|
|
uint32_t reserved_361; // offset: 361 (0x169)
|
|
uint32_t reserved_362; // offset: 362 (0x16A)
|
|
uint32_t reserved_363; // offset: 363 (0x16B)
|
|
uint32_t reserved_364; // offset: 364 (0x16C)
|
|
uint32_t reserved_365; // offset: 365 (0x16D)
|
|
uint32_t reserved_366; // offset: 366 (0x16E)
|
|
uint32_t reserved_367; // offset: 367 (0x16F)
|
|
uint32_t reserved_368; // offset: 368 (0x170)
|
|
uint32_t reserved_369; // offset: 369 (0x171)
|
|
uint32_t reserved_370; // offset: 370 (0x172)
|
|
uint32_t reserved_371; // offset: 371 (0x173)
|
|
uint32_t reserved_372; // offset: 372 (0x174)
|
|
uint32_t reserved_373; // offset: 373 (0x175)
|
|
uint32_t reserved_374; // offset: 374 (0x176)
|
|
uint32_t reserved_375; // offset: 375 (0x177)
|
|
uint32_t reserved_376; // offset: 376 (0x178)
|
|
uint32_t reserved_377; // offset: 377 (0x179)
|
|
uint32_t reserved_378; // offset: 378 (0x17A)
|
|
uint32_t reserved_379; // offset: 379 (0x17B)
|
|
uint32_t reserved_380; // offset: 380 (0x17C)
|
|
uint32_t reserved_381; // offset: 381 (0x17D)
|
|
uint32_t reserved_382; // offset: 382 (0x17E)
|
|
uint32_t reserved_383; // offset: 383 (0x17F)
|
|
uint32_t iqtimer_pkt_header; // offset: 384 (0x180)
|
|
uint32_t iqtimer_pkt_dw0; // offset: 385 (0x181)
|
|
uint32_t iqtimer_pkt_dw1; // offset: 386 (0x182)
|
|
uint32_t iqtimer_pkt_dw2; // offset: 387 (0x183)
|
|
uint32_t iqtimer_pkt_dw3; // offset: 388 (0x184)
|
|
uint32_t iqtimer_pkt_dw4; // offset: 389 (0x185)
|
|
uint32_t iqtimer_pkt_dw5; // offset: 390 (0x186)
|
|
uint32_t iqtimer_pkt_dw6; // offset: 391 (0x187)
|
|
uint32_t iqtimer_pkt_dw7; // offset: 392 (0x188)
|
|
uint32_t iqtimer_pkt_dw8; // offset: 393 (0x189)
|
|
uint32_t iqtimer_pkt_dw9; // offset: 394 (0x18A)
|
|
uint32_t iqtimer_pkt_dw10; // offset: 395 (0x18B)
|
|
uint32_t iqtimer_pkt_dw11; // offset: 396 (0x18C)
|
|
uint32_t iqtimer_pkt_dw12; // offset: 397 (0x18D)
|
|
uint32_t iqtimer_pkt_dw13; // offset: 398 (0x18E)
|
|
uint32_t iqtimer_pkt_dw14; // offset: 399 (0x18F)
|
|
uint32_t iqtimer_pkt_dw15; // offset: 400 (0x190)
|
|
uint32_t iqtimer_pkt_dw16; // offset: 401 (0x191)
|
|
uint32_t iqtimer_pkt_dw17; // offset: 402 (0x192)
|
|
uint32_t iqtimer_pkt_dw18; // offset: 403 (0x193)
|
|
uint32_t iqtimer_pkt_dw19; // offset: 404 (0x194)
|
|
uint32_t iqtimer_pkt_dw20; // offset: 405 (0x195)
|
|
uint32_t iqtimer_pkt_dw21; // offset: 406 (0x196)
|
|
uint32_t iqtimer_pkt_dw22; // offset: 407 (0x197)
|
|
uint32_t iqtimer_pkt_dw23; // offset: 408 (0x198)
|
|
uint32_t iqtimer_pkt_dw24; // offset: 409 (0x199)
|
|
uint32_t iqtimer_pkt_dw25; // offset: 410 (0x19A)
|
|
uint32_t iqtimer_pkt_dw26; // offset: 411 (0x19B)
|
|
uint32_t iqtimer_pkt_dw27; // offset: 412 (0x19C)
|
|
uint32_t iqtimer_pkt_dw28; // offset: 413 (0x19D)
|
|
uint32_t iqtimer_pkt_dw29; // offset: 414 (0x19E)
|
|
uint32_t iqtimer_pkt_dw30; // offset: 415 (0x19F)
|
|
uint32_t iqtimer_pkt_dw31; // offset: 416 (0x1A0)
|
|
uint32_t reserved_417; // offset: 417 (0x1A1)
|
|
uint32_t reserved_418; // offset: 418 (0x1A2)
|
|
uint32_t reserved_419; // offset: 419 (0x1A3)
|
|
uint32_t reserved_420; // offset: 420 (0x1A4)
|
|
uint32_t reserved_421; // offset: 421 (0x1A5)
|
|
uint32_t reserved_422; // offset: 422 (0x1A6)
|
|
uint32_t reserved_423; // offset: 423 (0x1A7)
|
|
uint32_t reserved_424; // offset: 424 (0x1A8)
|
|
uint32_t reserved_425; // offset: 425 (0x1A9)
|
|
uint32_t reserved_426; // offset: 426 (0x1AA)
|
|
uint32_t reserved_427; // offset: 427 (0x1AB)
|
|
uint32_t reserved_428; // offset: 428 (0x1AC)
|
|
uint32_t reserved_429; // offset: 429 (0x1AD)
|
|
uint32_t reserved_430; // offset: 430 (0x1AE)
|
|
uint32_t reserved_431; // offset: 431 (0x1AF)
|
|
uint32_t reserved_432; // offset: 432 (0x1B0)
|
|
uint32_t reserved_433; // offset: 433 (0x1B1)
|
|
uint32_t reserved_434; // offset: 434 (0x1B2)
|
|
uint32_t reserved_435; // offset: 435 (0x1B3)
|
|
uint32_t reserved_436; // offset: 436 (0x1B4)
|
|
uint32_t reserved_437; // offset: 437 (0x1B5)
|
|
uint32_t reserved_438; // offset: 438 (0x1B6)
|
|
uint32_t reserved_439; // offset: 439 (0x1B7)
|
|
uint32_t reserved_440; // offset: 440 (0x1B8)
|
|
uint32_t reserved_441; // offset: 441 (0x1B9)
|
|
uint32_t reserved_442; // offset: 442 (0x1BA)
|
|
uint32_t reserved_443; // offset: 443 (0x1BB)
|
|
uint32_t reserved_444; // offset: 444 (0x1BC)
|
|
uint32_t reserved_445; // offset: 445 (0x1BD)
|
|
uint32_t reserved_446; // offset: 446 (0x1BE)
|
|
uint32_t reserved_447; // offset: 447 (0x1BF)
|
|
uint32_t reserved_448; // offset: 448 (0x1C0)
|
|
uint32_t reserved_449; // offset: 449 (0x1C1)
|
|
uint32_t reserved_450; // offset: 450 (0x1C2)
|
|
uint32_t reserved_451; // offset: 451 (0x1C3)
|
|
uint32_t reserved_452; // offset: 452 (0x1C4)
|
|
uint32_t reserved_453; // offset: 453 (0x1C5)
|
|
uint32_t reserved_454; // offset: 454 (0x1C6)
|
|
uint32_t reserved_455; // offset: 455 (0x1C7)
|
|
uint32_t reserved_456; // offset: 456 (0x1C8)
|
|
uint32_t reserved_457; // offset: 457 (0x1C9)
|
|
uint32_t reserved_458; // offset: 458 (0x1CA)
|
|
uint32_t reserved_459; // offset: 459 (0x1CB)
|
|
uint32_t reserved_460; // offset: 460 (0x1CC)
|
|
uint32_t reserved_461; // offset: 461 (0x1CD)
|
|
uint32_t reserved_462; // offset: 462 (0x1CE)
|
|
uint32_t reserved_463; // offset: 463 (0x1CF)
|
|
uint32_t reserved_464; // offset: 464 (0x1D0)
|
|
uint32_t reserved_465; // offset: 465 (0x1D1)
|
|
uint32_t reserved_466; // offset: 466 (0x1D2)
|
|
uint32_t reserved_467; // offset: 467 (0x1D3)
|
|
uint32_t reserved_468; // offset: 468 (0x1D4)
|
|
uint32_t reserved_469; // offset: 469 (0x1D5)
|
|
uint32_t reserved_470; // offset: 470 (0x1D6)
|
|
uint32_t reserved_471; // offset: 471 (0x1D7)
|
|
uint32_t reserved_472; // offset: 472 (0x1D8)
|
|
uint32_t reserved_473; // offset: 473 (0x1D9)
|
|
uint32_t reserved_474; // offset: 474 (0x1DA)
|
|
uint32_t reserved_475; // offset: 475 (0x1DB)
|
|
uint32_t reserved_476; // offset: 476 (0x1DC)
|
|
uint32_t reserved_477; // offset: 477 (0x1DD)
|
|
uint32_t reserved_478; // offset: 478 (0x1DE)
|
|
uint32_t reserved_479; // offset: 479 (0x1DF)
|
|
uint32_t reserved_480; // offset: 480 (0x1E0)
|
|
uint32_t reserved_481; // offset: 481 (0x1E1)
|
|
uint32_t reserved_482; // offset: 482 (0x1E2)
|
|
uint32_t reserved_483; // offset: 483 (0x1E3)
|
|
uint32_t reserved_484; // offset: 484 (0x1E4)
|
|
uint32_t reserved_485; // offset: 485 (0x1E5)
|
|
uint32_t reserved_486; // offset: 486 (0x1E6)
|
|
uint32_t reserved_487; // offset: 487 (0x1E7)
|
|
uint32_t reserved_488; // offset: 488 (0x1E8)
|
|
uint32_t reserved_489; // offset: 489 (0x1E9)
|
|
uint32_t reserved_490; // offset: 490 (0x1EA)
|
|
uint32_t reserved_491; // offset: 491 (0x1EB)
|
|
uint32_t reserved_492; // offset: 492 (0x1EC)
|
|
uint32_t reserved_493; // offset: 493 (0x1ED)
|
|
uint32_t reserved_494; // offset: 494 (0x1EE)
|
|
uint32_t reserved_495; // offset: 495 (0x1EF)
|
|
uint32_t reserved_496; // offset: 496 (0x1F0)
|
|
uint32_t reserved_497; // offset: 497 (0x1F1)
|
|
uint32_t reserved_498; // offset: 498 (0x1F2)
|
|
uint32_t reserved_499; // offset: 499 (0x1F3)
|
|
uint32_t reserved_500; // offset: 500 (0x1F4)
|
|
uint32_t reserved_501; // offset: 501 (0x1F5)
|
|
uint32_t reserved_502; // offset: 502 (0x1F6)
|
|
uint32_t reserved_503; // offset: 503 (0x1F7)
|
|
uint32_t reserved_504; // offset: 504 (0x1F8)
|
|
uint32_t reserved_505; // offset: 505 (0x1F9)
|
|
uint32_t reserved_506; // offset: 506 (0x1FA)
|
|
uint32_t reserved_507; // offset: 507 (0x1FB)
|
|
uint32_t reserved_508; // offset: 508 (0x1FC)
|
|
uint32_t reserved_509; // offset: 509 (0x1FD)
|
|
uint32_t reserved_510; // offset: 510 (0x1FE)
|
|
uint32_t reserved_511; // offset: 511 (0x1FF)
|
|
uint32_t reserved_512; // offset: 512 (0x200)
|
|
uint32_t reserved_513; // offset: 513 (0x201)
|
|
uint32_t reserved_514; // offset: 514 (0x202)
|
|
uint32_t reserved_515; // offset: 515 (0x203)
|
|
uint32_t reserved_516; // offset: 516 (0x204)
|
|
uint32_t reserved_517; // offset: 517 (0x205)
|
|
uint32_t reserved_518; // offset: 518 (0x206)
|
|
uint32_t reserved_519; // offset: 519 (0x207)
|
|
uint32_t reserved_520; // offset: 520 (0x208)
|
|
uint32_t reserved_521; // offset: 521 (0x209)
|
|
uint32_t reserved_522; // offset: 522 (0x20A)
|
|
uint32_t reserved_523; // offset: 523 (0x20B)
|
|
uint32_t reserved_524; // offset: 524 (0x20C)
|
|
uint32_t reserved_525; // offset: 525 (0x20D)
|
|
uint32_t reserved_526; // offset: 526 (0x20E)
|
|
uint32_t reserved_527; // offset: 527 (0x20F)
|
|
uint32_t reserved_528; // offset: 528 (0x210)
|
|
uint32_t reserved_529; // offset: 529 (0x211)
|
|
uint32_t reserved_530; // offset: 530 (0x212)
|
|
uint32_t reserved_531; // offset: 531 (0x213)
|
|
uint32_t reserved_532; // offset: 532 (0x214)
|
|
uint32_t reserved_533; // offset: 533 (0x215)
|
|
uint32_t reserved_534; // offset: 534 (0x216)
|
|
uint32_t reserved_535; // offset: 535 (0x217)
|
|
uint32_t reserved_536; // offset: 536 (0x218)
|
|
uint32_t reserved_537; // offset: 537 (0x219)
|
|
uint32_t reserved_538; // offset: 538 (0x21A)
|
|
uint32_t reserved_539; // offset: 539 (0x21B)
|
|
uint32_t reserved_540; // offset: 540 (0x21C)
|
|
uint32_t reserved_541; // offset: 541 (0x21D)
|
|
uint32_t reserved_542; // offset: 542 (0x21E)
|
|
uint32_t reserved_543; // offset: 543 (0x21F)
|
|
uint32_t reserved_544; // offset: 544 (0x220)
|
|
uint32_t reserved_545; // offset: 545 (0x221)
|
|
uint32_t reserved_546; // offset: 546 (0x222)
|
|
uint32_t reserved_547; // offset: 547 (0x223)
|
|
uint32_t reserved_548; // offset: 548 (0x224)
|
|
uint32_t reserved_549; // offset: 549 (0x225)
|
|
uint32_t reserved_550; // offset: 550 (0x226)
|
|
uint32_t reserved_551; // offset: 551 (0x227)
|
|
uint32_t reserved_552; // offset: 552 (0x228)
|
|
uint32_t reserved_553; // offset: 553 (0x229)
|
|
uint32_t reserved_554; // offset: 554 (0x22A)
|
|
uint32_t reserved_555; // offset: 555 (0x22B)
|
|
uint32_t reserved_556; // offset: 556 (0x22C)
|
|
uint32_t reserved_557; // offset: 557 (0x22D)
|
|
uint32_t reserved_558; // offset: 558 (0x22E)
|
|
uint32_t reserved_559; // offset: 559 (0x22F)
|
|
uint32_t reserved_560; // offset: 560 (0x230)
|
|
uint32_t reserved_561; // offset: 561 (0x231)
|
|
uint32_t reserved_562; // offset: 562 (0x232)
|
|
uint32_t reserved_563; // offset: 563 (0x233)
|
|
uint32_t reserved_564; // offset: 564 (0x234)
|
|
uint32_t reserved_565; // offset: 565 (0x235)
|
|
uint32_t reserved_566; // offset: 566 (0x236)
|
|
uint32_t reserved_567; // offset: 567 (0x237)
|
|
uint32_t reserved_568; // offset: 568 (0x238)
|
|
uint32_t reserved_569; // offset: 569 (0x239)
|
|
uint32_t reserved_570; // offset: 570 (0x23A)
|
|
uint32_t reserved_571; // offset: 571 (0x23B)
|
|
uint32_t reserved_572; // offset: 572 (0x23C)
|
|
uint32_t reserved_573; // offset: 573 (0x23D)
|
|
uint32_t reserved_574; // offset: 574 (0x23E)
|
|
uint32_t reserved_575; // offset: 575 (0x23F)
|
|
uint32_t reserved_576; // offset: 576 (0x240)
|
|
uint32_t reserved_577; // offset: 577 (0x241)
|
|
uint32_t reserved_578; // offset: 578 (0x242)
|
|
uint32_t reserved_579; // offset: 579 (0x243)
|
|
uint32_t reserved_580; // offset: 580 (0x244)
|
|
uint32_t reserved_581; // offset: 581 (0x245)
|
|
uint32_t reserved_582; // offset: 582 (0x246)
|
|
uint32_t reserved_583; // offset: 583 (0x247)
|
|
uint32_t reserved_584; // offset: 584 (0x248)
|
|
uint32_t reserved_585; // offset: 585 (0x249)
|
|
uint32_t reserved_586; // offset: 586 (0x24A)
|
|
uint32_t reserved_587; // offset: 587 (0x24B)
|
|
uint32_t reserved_588; // offset: 588 (0x24C)
|
|
uint32_t reserved_589; // offset: 589 (0x24D)
|
|
uint32_t reserved_590; // offset: 590 (0x24E)
|
|
uint32_t reserved_591; // offset: 591 (0x24F)
|
|
uint32_t reserved_592; // offset: 592 (0x250)
|
|
uint32_t reserved_593; // offset: 593 (0x251)
|
|
uint32_t reserved_594; // offset: 594 (0x252)
|
|
uint32_t reserved_595; // offset: 595 (0x253)
|
|
uint32_t reserved_596; // offset: 596 (0x254)
|
|
uint32_t reserved_597; // offset: 597 (0x255)
|
|
uint32_t reserved_598; // offset: 598 (0x256)
|
|
uint32_t reserved_599; // offset: 599 (0x257)
|
|
uint32_t reserved_600; // offset: 600 (0x258)
|
|
uint32_t reserved_601; // offset: 601 (0x259)
|
|
uint32_t reserved_602; // offset: 602 (0x25A)
|
|
uint32_t reserved_603; // offset: 603 (0x25B)
|
|
uint32_t reserved_604; // offset: 604 (0x25C)
|
|
uint32_t reserved_605; // offset: 605 (0x25D)
|
|
uint32_t reserved_606; // offset: 606 (0x25E)
|
|
uint32_t reserved_607; // offset: 607 (0x25F)
|
|
uint32_t reserved_608; // offset: 608 (0x260)
|
|
uint32_t reserved_609; // offset: 609 (0x261)
|
|
uint32_t reserved_610; // offset: 610 (0x262)
|
|
uint32_t reserved_611; // offset: 611 (0x263)
|
|
uint32_t reserved_612; // offset: 612 (0x264)
|
|
uint32_t reserved_613; // offset: 613 (0x265)
|
|
uint32_t reserved_614; // offset: 614 (0x266)
|
|
uint32_t reserved_615; // offset: 615 (0x267)
|
|
uint32_t reserved_616; // offset: 616 (0x268)
|
|
uint32_t reserved_617; // offset: 617 (0x269)
|
|
uint32_t reserved_618; // offset: 618 (0x26A)
|
|
uint32_t reserved_619; // offset: 619 (0x26B)
|
|
uint32_t reserved_620; // offset: 620 (0x26C)
|
|
uint32_t reserved_621; // offset: 621 (0x26D)
|
|
uint32_t reserved_622; // offset: 622 (0x26E)
|
|
uint32_t reserved_623; // offset: 623 (0x26F)
|
|
uint32_t reserved_624; // offset: 624 (0x270)
|
|
uint32_t reserved_625; // offset: 625 (0x271)
|
|
uint32_t reserved_626; // offset: 626 (0x272)
|
|
uint32_t reserved_627; // offset: 627 (0x273)
|
|
uint32_t reserved_628; // offset: 628 (0x274)
|
|
uint32_t reserved_629; // offset: 629 (0x275)
|
|
uint32_t reserved_630; // offset: 630 (0x276)
|
|
uint32_t reserved_631; // offset: 631 (0x277)
|
|
uint32_t reserved_632; // offset: 632 (0x278)
|
|
uint32_t reserved_633; // offset: 633 (0x279)
|
|
uint32_t reserved_634; // offset: 634 (0x27A)
|
|
uint32_t reserved_635; // offset: 635 (0x27B)
|
|
uint32_t reserved_636; // offset: 636 (0x27C)
|
|
uint32_t reserved_637; // offset: 637 (0x27D)
|
|
uint32_t reserved_638; // offset: 638 (0x27E)
|
|
uint32_t reserved_639; // offset: 639 (0x27F)
|
|
uint32_t reserved_640; // offset: 640 (0x280)
|
|
uint32_t reserved_641; // offset: 641 (0x281)
|
|
uint32_t reserved_642; // offset: 642 (0x282)
|
|
uint32_t reserved_643; // offset: 643 (0x283)
|
|
uint32_t reserved_644; // offset: 644 (0x284)
|
|
uint32_t reserved_645; // offset: 645 (0x285)
|
|
uint32_t reserved_646; // offset: 646 (0x286)
|
|
uint32_t reserved_647; // offset: 647 (0x287)
|
|
uint32_t reserved_648; // offset: 648 (0x288)
|
|
uint32_t reserved_649; // offset: 649 (0x289)
|
|
uint32_t reserved_650; // offset: 650 (0x28A)
|
|
uint32_t reserved_651; // offset: 651 (0x28B)
|
|
uint32_t reserved_652; // offset: 652 (0x28C)
|
|
uint32_t reserved_653; // offset: 653 (0x28D)
|
|
uint32_t reserved_654; // offset: 654 (0x28E)
|
|
uint32_t reserved_655; // offset: 655 (0x28F)
|
|
uint32_t reserved_656; // offset: 656 (0x290)
|
|
uint32_t reserved_657; // offset: 657 (0x291)
|
|
uint32_t reserved_658; // offset: 658 (0x292)
|
|
uint32_t reserved_659; // offset: 659 (0x293)
|
|
uint32_t reserved_660; // offset: 660 (0x294)
|
|
uint32_t reserved_661; // offset: 661 (0x295)
|
|
uint32_t reserved_662; // offset: 662 (0x296)
|
|
uint32_t reserved_663; // offset: 663 (0x297)
|
|
uint32_t reserved_664; // offset: 664 (0x298)
|
|
uint32_t reserved_665; // offset: 665 (0x299)
|
|
uint32_t reserved_666; // offset: 666 (0x29A)
|
|
uint32_t reserved_667; // offset: 667 (0x29B)
|
|
uint32_t reserved_668; // offset: 668 (0x29C)
|
|
uint32_t reserved_669; // offset: 669 (0x29D)
|
|
uint32_t reserved_670; // offset: 670 (0x29E)
|
|
uint32_t reserved_671; // offset: 671 (0x29F)
|
|
uint32_t reserved_672; // offset: 672 (0x2A0)
|
|
uint32_t reserved_673; // offset: 673 (0x2A1)
|
|
uint32_t reserved_674; // offset: 674 (0x2A2)
|
|
uint32_t reserved_675; // offset: 675 (0x2A3)
|
|
uint32_t reserved_676; // offset: 676 (0x2A4)
|
|
uint32_t reserved_677; // offset: 677 (0x2A5)
|
|
uint32_t reserved_678; // offset: 678 (0x2A6)
|
|
uint32_t reserved_679; // offset: 679 (0x2A7)
|
|
uint32_t reserved_680; // offset: 680 (0x2A8)
|
|
uint32_t reserved_681; // offset: 681 (0x2A9)
|
|
uint32_t reserved_682; // offset: 682 (0x2AA)
|
|
uint32_t reserved_683; // offset: 683 (0x2AB)
|
|
uint32_t reserved_684; // offset: 684 (0x2AC)
|
|
uint32_t reserved_685; // offset: 685 (0x2AD)
|
|
uint32_t reserved_686; // offset: 686 (0x2AE)
|
|
uint32_t reserved_687; // offset: 687 (0x2AF)
|
|
uint32_t reserved_688; // offset: 688 (0x2B0)
|
|
uint32_t reserved_689; // offset: 689 (0x2B1)
|
|
uint32_t reserved_690; // offset: 690 (0x2B2)
|
|
uint32_t reserved_691; // offset: 691 (0x2B3)
|
|
uint32_t reserved_692; // offset: 692 (0x2B4)
|
|
uint32_t reserved_693; // offset: 693 (0x2B5)
|
|
uint32_t reserved_694; // offset: 694 (0x2B6)
|
|
uint32_t reserved_695; // offset: 695 (0x2B7)
|
|
uint32_t reserved_696; // offset: 696 (0x2B8)
|
|
uint32_t reserved_697; // offset: 697 (0x2B9)
|
|
uint32_t reserved_698; // offset: 698 (0x2BA)
|
|
uint32_t reserved_699; // offset: 699 (0x2BB)
|
|
uint32_t reserved_700; // offset: 700 (0x2BC)
|
|
uint32_t reserved_701; // offset: 701 (0x2BD)
|
|
uint32_t reserved_702; // offset: 702 (0x2BE)
|
|
uint32_t reserved_703; // offset: 703 (0x2BF)
|
|
uint32_t reserved_704; // offset: 704 (0x2C0)
|
|
uint32_t reserved_705; // offset: 705 (0x2C1)
|
|
uint32_t reserved_706; // offset: 706 (0x2C2)
|
|
uint32_t reserved_707; // offset: 707 (0x2C3)
|
|
uint32_t reserved_708; // offset: 708 (0x2C4)
|
|
uint32_t reserved_709; // offset: 709 (0x2C5)
|
|
uint32_t reserved_710; // offset: 710 (0x2C6)
|
|
uint32_t reserved_711; // offset: 711 (0x2C7)
|
|
uint32_t reserved_712; // offset: 712 (0x2C8)
|
|
uint32_t reserved_713; // offset: 713 (0x2C9)
|
|
uint32_t reserved_714; // offset: 714 (0x2CA)
|
|
uint32_t reserved_715; // offset: 715 (0x2CB)
|
|
uint32_t reserved_716; // offset: 716 (0x2CC)
|
|
uint32_t reserved_717; // offset: 717 (0x2CD)
|
|
uint32_t reserved_718; // offset: 718 (0x2CE)
|
|
uint32_t reserved_719; // offset: 719 (0x2CF)
|
|
uint32_t reserved_720; // offset: 720 (0x2D0)
|
|
uint32_t reserved_721; // offset: 721 (0x2D1)
|
|
uint32_t reserved_722; // offset: 722 (0x2D2)
|
|
uint32_t reserved_723; // offset: 723 (0x2D3)
|
|
uint32_t reserved_724; // offset: 724 (0x2D4)
|
|
uint32_t reserved_725; // offset: 725 (0x2D5)
|
|
uint32_t reserved_726; // offset: 726 (0x2D6)
|
|
uint32_t reserved_727; // offset: 727 (0x2D7)
|
|
uint32_t reserved_728; // offset: 728 (0x2D8)
|
|
uint32_t reserved_729; // offset: 729 (0x2D9)
|
|
uint32_t reserved_730; // offset: 730 (0x2DA)
|
|
uint32_t reserved_731; // offset: 731 (0x2DB)
|
|
uint32_t reserved_732; // offset: 732 (0x2DC)
|
|
uint32_t reserved_733; // offset: 733 (0x2DD)
|
|
uint32_t reserved_734; // offset: 734 (0x2DE)
|
|
uint32_t reserved_735; // offset: 735 (0x2DF)
|
|
uint32_t reserved_736; // offset: 736 (0x2E0)
|
|
uint32_t reserved_737; // offset: 737 (0x2E1)
|
|
uint32_t reserved_738; // offset: 738 (0x2E2)
|
|
uint32_t reserved_739; // offset: 739 (0x2E3)
|
|
uint32_t reserved_740; // offset: 740 (0x2E4)
|
|
uint32_t reserved_741; // offset: 741 (0x2E5)
|
|
uint32_t reserved_742; // offset: 742 (0x2E6)
|
|
uint32_t reserved_743; // offset: 743 (0x2E7)
|
|
uint32_t reserved_744; // offset: 744 (0x2E8)
|
|
uint32_t reserved_745; // offset: 745 (0x2E9)
|
|
uint32_t reserved_746; // offset: 746 (0x2EA)
|
|
uint32_t reserved_747; // offset: 747 (0x2EB)
|
|
uint32_t reserved_748; // offset: 748 (0x2EC)
|
|
uint32_t reserved_749; // offset: 749 (0x2ED)
|
|
uint32_t reserved_750; // offset: 750 (0x2EE)
|
|
uint32_t reserved_751; // offset: 751 (0x2EF)
|
|
uint32_t reserved_752; // offset: 752 (0x2F0)
|
|
uint32_t reserved_753; // offset: 753 (0x2F1)
|
|
uint32_t reserved_754; // offset: 754 (0x2F2)
|
|
uint32_t reserved_755; // offset: 755 (0x2F3)
|
|
uint32_t reserved_756; // offset: 756 (0x2F4)
|
|
uint32_t reserved_757; // offset: 757 (0x2F5)
|
|
uint32_t reserved_758; // offset: 758 (0x2F6)
|
|
uint32_t reserved_759; // offset: 759 (0x2F7)
|
|
uint32_t reserved_760; // offset: 760 (0x2F8)
|
|
uint32_t reserved_761; // offset: 761 (0x2F9)
|
|
uint32_t reserved_762; // offset: 762 (0x2FA)
|
|
uint32_t reserved_763; // offset: 763 (0x2FB)
|
|
uint32_t reserved_764; // offset: 764 (0x2FC)
|
|
uint32_t reserved_765; // offset: 765 (0x2FD)
|
|
uint32_t reserved_766; // offset: 766 (0x2FE)
|
|
uint32_t reserved_767; // offset: 767 (0x2FF)
|
|
uint32_t reserved_768; // offset: 768 (0x300)
|
|
uint32_t reserved_769; // offset: 769 (0x301)
|
|
uint32_t reserved_770; // offset: 770 (0x302)
|
|
uint32_t reserved_771; // offset: 771 (0x303)
|
|
uint32_t reserved_772; // offset: 772 (0x304)
|
|
uint32_t reserved_773; // offset: 773 (0x305)
|
|
uint32_t reserved_774; // offset: 774 (0x306)
|
|
uint32_t reserved_775; // offset: 775 (0x307)
|
|
uint32_t reserved_776; // offset: 776 (0x308)
|
|
uint32_t reserved_777; // offset: 777 (0x309)
|
|
uint32_t reserved_778; // offset: 778 (0x30A)
|
|
uint32_t reserved_779; // offset: 779 (0x30B)
|
|
uint32_t reserved_780; // offset: 780 (0x30C)
|
|
uint32_t reserved_781; // offset: 781 (0x30D)
|
|
uint32_t reserved_782; // offset: 782 (0x30E)
|
|
uint32_t reserved_783; // offset: 783 (0x30F)
|
|
uint32_t reserved_784; // offset: 784 (0x310)
|
|
uint32_t reserved_785; // offset: 785 (0x311)
|
|
uint32_t reserved_786; // offset: 786 (0x312)
|
|
uint32_t reserved_787; // offset: 787 (0x313)
|
|
uint32_t reserved_788; // offset: 788 (0x314)
|
|
uint32_t reserved_789; // offset: 789 (0x315)
|
|
uint32_t reserved_790; // offset: 790 (0x316)
|
|
uint32_t reserved_791; // offset: 791 (0x317)
|
|
uint32_t reserved_792; // offset: 792 (0x318)
|
|
uint32_t reserved_793; // offset: 793 (0x319)
|
|
uint32_t reserved_794; // offset: 794 (0x31A)
|
|
uint32_t reserved_795; // offset: 795 (0x31B)
|
|
uint32_t reserved_796; // offset: 796 (0x31C)
|
|
uint32_t reserved_797; // offset: 797 (0x31D)
|
|
uint32_t reserved_798; // offset: 798 (0x31E)
|
|
uint32_t reserved_799; // offset: 799 (0x31F)
|
|
uint32_t reserved_800; // offset: 800 (0x320)
|
|
uint32_t reserved_801; // offset: 801 (0x321)
|
|
uint32_t reserved_802; // offset: 802 (0x322)
|
|
uint32_t reserved_803; // offset: 803 (0x323)
|
|
uint32_t reserved_804; // offset: 804 (0x324)
|
|
uint32_t reserved_805; // offset: 805 (0x325)
|
|
uint32_t reserved_806; // offset: 806 (0x326)
|
|
uint32_t reserved_807; // offset: 807 (0x327)
|
|
uint32_t reserved_808; // offset: 808 (0x328)
|
|
uint32_t reserved_809; // offset: 809 (0x329)
|
|
uint32_t reserved_810; // offset: 810 (0x32A)
|
|
uint32_t reserved_811; // offset: 811 (0x32B)
|
|
uint32_t reserved_812; // offset: 812 (0x32C)
|
|
uint32_t reserved_813; // offset: 813 (0x32D)
|
|
uint32_t reserved_814; // offset: 814 (0x32E)
|
|
uint32_t reserved_815; // offset: 815 (0x32F)
|
|
uint32_t reserved_816; // offset: 816 (0x330)
|
|
uint32_t reserved_817; // offset: 817 (0x331)
|
|
uint32_t reserved_818; // offset: 818 (0x332)
|
|
uint32_t reserved_819; // offset: 819 (0x333)
|
|
uint32_t reserved_820; // offset: 820 (0x334)
|
|
uint32_t reserved_821; // offset: 821 (0x335)
|
|
uint32_t reserved_822; // offset: 822 (0x336)
|
|
uint32_t reserved_823; // offset: 823 (0x337)
|
|
uint32_t reserved_824; // offset: 824 (0x338)
|
|
uint32_t reserved_825; // offset: 825 (0x339)
|
|
uint32_t reserved_826; // offset: 826 (0x33A)
|
|
uint32_t reserved_827; // offset: 827 (0x33B)
|
|
uint32_t reserved_828; // offset: 828 (0x33C)
|
|
uint32_t reserved_829; // offset: 829 (0x33D)
|
|
uint32_t reserved_830; // offset: 830 (0x33E)
|
|
uint32_t reserved_831; // offset: 831 (0x33F)
|
|
uint32_t reserved_832; // offset: 832 (0x340)
|
|
uint32_t reserved_833; // offset: 833 (0x341)
|
|
uint32_t reserved_834; // offset: 834 (0x342)
|
|
uint32_t reserved_835; // offset: 835 (0x343)
|
|
uint32_t reserved_836; // offset: 836 (0x344)
|
|
uint32_t reserved_837; // offset: 837 (0x345)
|
|
uint32_t reserved_838; // offset: 838 (0x346)
|
|
uint32_t reserved_839; // offset: 839 (0x347)
|
|
uint32_t reserved_840; // offset: 840 (0x348)
|
|
uint32_t reserved_841; // offset: 841 (0x349)
|
|
uint32_t reserved_842; // offset: 842 (0x34A)
|
|
uint32_t reserved_843; // offset: 843 (0x34B)
|
|
uint32_t reserved_844; // offset: 844 (0x34C)
|
|
uint32_t reserved_845; // offset: 845 (0x34D)
|
|
uint32_t reserved_846; // offset: 846 (0x34E)
|
|
uint32_t reserved_847; // offset: 847 (0x34F)
|
|
uint32_t reserved_848; // offset: 848 (0x350)
|
|
uint32_t reserved_849; // offset: 849 (0x351)
|
|
uint32_t reserved_850; // offset: 850 (0x352)
|
|
uint32_t reserved_851; // offset: 851 (0x353)
|
|
uint32_t reserved_852; // offset: 852 (0x354)
|
|
uint32_t reserved_853; // offset: 853 (0x355)
|
|
uint32_t reserved_854; // offset: 854 (0x356)
|
|
uint32_t reserved_855; // offset: 855 (0x357)
|
|
uint32_t reserved_856; // offset: 856 (0x358)
|
|
uint32_t reserved_857; // offset: 857 (0x359)
|
|
uint32_t reserved_858; // offset: 858 (0x35A)
|
|
uint32_t reserved_859; // offset: 859 (0x35B)
|
|
uint32_t reserved_860; // offset: 860 (0x35C)
|
|
uint32_t reserved_861; // offset: 861 (0x35D)
|
|
uint32_t reserved_862; // offset: 862 (0x35E)
|
|
uint32_t reserved_863; // offset: 863 (0x35F)
|
|
uint32_t reserved_864; // offset: 864 (0x360)
|
|
uint32_t reserved_865; // offset: 865 (0x361)
|
|
uint32_t reserved_866; // offset: 866 (0x362)
|
|
uint32_t reserved_867; // offset: 867 (0x363)
|
|
uint32_t reserved_868; // offset: 868 (0x364)
|
|
uint32_t reserved_869; // offset: 869 (0x365)
|
|
uint32_t reserved_870; // offset: 870 (0x366)
|
|
uint32_t reserved_871; // offset: 871 (0x367)
|
|
uint32_t reserved_872; // offset: 872 (0x368)
|
|
uint32_t reserved_873; // offset: 873 (0x369)
|
|
uint32_t reserved_874; // offset: 874 (0x36A)
|
|
uint32_t reserved_875; // offset: 875 (0x36B)
|
|
uint32_t reserved_876; // offset: 876 (0x36C)
|
|
uint32_t reserved_877; // offset: 877 (0x36D)
|
|
uint32_t reserved_878; // offset: 878 (0x36E)
|
|
uint32_t reserved_879; // offset: 879 (0x36F)
|
|
uint32_t reserved_880; // offset: 880 (0x370)
|
|
uint32_t reserved_881; // offset: 881 (0x371)
|
|
uint32_t reserved_882; // offset: 882 (0x372)
|
|
uint32_t reserved_883; // offset: 883 (0x373)
|
|
uint32_t reserved_884; // offset: 884 (0x374)
|
|
uint32_t reserved_885; // offset: 885 (0x375)
|
|
uint32_t reserved_886; // offset: 886 (0x376)
|
|
uint32_t reserved_887; // offset: 887 (0x377)
|
|
uint32_t reserved_888; // offset: 888 (0x378)
|
|
uint32_t reserved_889; // offset: 889 (0x379)
|
|
uint32_t reserved_890; // offset: 890 (0x37A)
|
|
uint32_t reserved_891; // offset: 891 (0x37B)
|
|
uint32_t reserved_892; // offset: 892 (0x37C)
|
|
uint32_t reserved_893; // offset: 893 (0x37D)
|
|
uint32_t reserved_894; // offset: 894 (0x37E)
|
|
uint32_t reserved_895; // offset: 895 (0x37F)
|
|
uint32_t reserved_896; // offset: 896 (0x380)
|
|
uint32_t reserved_897; // offset: 897 (0x381)
|
|
uint32_t reserved_898; // offset: 898 (0x382)
|
|
uint32_t reserved_899; // offset: 899 (0x383)
|
|
uint32_t reserved_900; // offset: 900 (0x384)
|
|
uint32_t reserved_901; // offset: 901 (0x385)
|
|
uint32_t reserved_902; // offset: 902 (0x386)
|
|
uint32_t reserved_903; // offset: 903 (0x387)
|
|
uint32_t reserved_904; // offset: 904 (0x388)
|
|
uint32_t reserved_905; // offset: 905 (0x389)
|
|
uint32_t reserved_906; // offset: 906 (0x38A)
|
|
uint32_t reserved_907; // offset: 907 (0x38B)
|
|
uint32_t reserved_908; // offset: 908 (0x38C)
|
|
uint32_t reserved_909; // offset: 909 (0x38D)
|
|
uint32_t reserved_910; // offset: 910 (0x38E)
|
|
uint32_t reserved_911; // offset: 911 (0x38F)
|
|
uint32_t reserved_912; // offset: 912 (0x390)
|
|
uint32_t reserved_913; // offset: 913 (0x391)
|
|
uint32_t reserved_914; // offset: 914 (0x392)
|
|
uint32_t reserved_915; // offset: 915 (0x393)
|
|
uint32_t reserved_916; // offset: 916 (0x394)
|
|
uint32_t reserved_917; // offset: 917 (0x395)
|
|
uint32_t reserved_918; // offset: 918 (0x396)
|
|
uint32_t reserved_919; // offset: 919 (0x397)
|
|
uint32_t reserved_920; // offset: 920 (0x398)
|
|
uint32_t reserved_921; // offset: 921 (0x399)
|
|
uint32_t reserved_922; // offset: 922 (0x39A)
|
|
uint32_t reserved_923; // offset: 923 (0x39B)
|
|
uint32_t reserved_924; // offset: 924 (0x39C)
|
|
uint32_t reserved_925; // offset: 925 (0x39D)
|
|
uint32_t reserved_926; // offset: 926 (0x39E)
|
|
uint32_t reserved_927; // offset: 927 (0x39F)
|
|
uint32_t reserved_928; // offset: 928 (0x3A0)
|
|
uint32_t reserved_929; // offset: 929 (0x3A1)
|
|
uint32_t reserved_930; // offset: 930 (0x3A2)
|
|
uint32_t reserved_931; // offset: 931 (0x3A3)
|
|
uint32_t reserved_932; // offset: 932 (0x3A4)
|
|
uint32_t reserved_933; // offset: 933 (0x3A5)
|
|
uint32_t reserved_934; // offset: 934 (0x3A6)
|
|
uint32_t reserved_935; // offset: 935 (0x3A7)
|
|
uint32_t reserved_936; // offset: 936 (0x3A8)
|
|
uint32_t reserved_937; // offset: 937 (0x3A9)
|
|
uint32_t reserved_938; // offset: 938 (0x3AA)
|
|
uint32_t reserved_939; // offset: 939 (0x3AB)
|
|
uint32_t reserved_940; // offset: 940 (0x3AC)
|
|
uint32_t reserved_941; // offset: 941 (0x3AD)
|
|
uint32_t reserved_942; // offset: 942 (0x3AE)
|
|
uint32_t reserved_943; // offset: 943 (0x3AF)
|
|
uint32_t reserved_944; // offset: 944 (0x3B0)
|
|
uint32_t reserved_945; // offset: 945 (0x3B1)
|
|
uint32_t reserved_946; // offset: 946 (0x3B2)
|
|
uint32_t reserved_947; // offset: 947 (0x3B3)
|
|
uint32_t reserved_948; // offset: 948 (0x3B4)
|
|
uint32_t reserved_949; // offset: 949 (0x3B5)
|
|
uint32_t reserved_950; // offset: 950 (0x3B6)
|
|
uint32_t reserved_951; // offset: 951 (0x3B7)
|
|
uint32_t reserved_952; // offset: 952 (0x3B8)
|
|
uint32_t reserved_953; // offset: 953 (0x3B9)
|
|
uint32_t reserved_954; // offset: 954 (0x3BA)
|
|
uint32_t reserved_955; // offset: 955 (0x3BB)
|
|
uint32_t reserved_956; // offset: 956 (0x3BC)
|
|
uint32_t reserved_957; // offset: 957 (0x3BD)
|
|
uint32_t reserved_958; // offset: 958 (0x3BE)
|
|
uint32_t reserved_959; // offset: 959 (0x3BF)
|
|
uint32_t reserved_960; // offset: 960 (0x3C0)
|
|
uint32_t reserved_961; // offset: 961 (0x3C1)
|
|
uint32_t reserved_962; // offset: 962 (0x3C2)
|
|
uint32_t reserved_963; // offset: 963 (0x3C3)
|
|
uint32_t reserved_964; // offset: 964 (0x3C4)
|
|
uint32_t reserved_965; // offset: 965 (0x3C5)
|
|
uint32_t reserved_966; // offset: 966 (0x3C6)
|
|
uint32_t reserved_967; // offset: 967 (0x3C7)
|
|
uint32_t reserved_968; // offset: 968 (0x3C8)
|
|
uint32_t reserved_969; // offset: 969 (0x3C9)
|
|
uint32_t reserved_970; // offset: 970 (0x3CA)
|
|
uint32_t reserved_971; // offset: 971 (0x3CB)
|
|
uint32_t reserved_972; // offset: 972 (0x3CC)
|
|
uint32_t reserved_973; // offset: 973 (0x3CD)
|
|
uint32_t reserved_974; // offset: 974 (0x3CE)
|
|
uint32_t reserved_975; // offset: 975 (0x3CF)
|
|
uint32_t reserved_976; // offset: 976 (0x3D0)
|
|
uint32_t reserved_977; // offset: 977 (0x3D1)
|
|
uint32_t reserved_978; // offset: 978 (0x3D2)
|
|
uint32_t reserved_979; // offset: 979 (0x3D3)
|
|
uint32_t reserved_980; // offset: 980 (0x3D4)
|
|
uint32_t reserved_981; // offset: 981 (0x3D5)
|
|
uint32_t reserved_982; // offset: 982 (0x3D6)
|
|
uint32_t reserved_983; // offset: 983 (0x3D7)
|
|
uint32_t reserved_984; // offset: 984 (0x3D8)
|
|
uint32_t reserved_985; // offset: 985 (0x3D9)
|
|
uint32_t reserved_986; // offset: 986 (0x3DA)
|
|
uint32_t reserved_987; // offset: 987 (0x3DB)
|
|
uint32_t reserved_988; // offset: 988 (0x3DC)
|
|
uint32_t reserved_989; // offset: 989 (0x3DD)
|
|
uint32_t reserved_990; // offset: 990 (0x3DE)
|
|
uint32_t reserved_991; // offset: 991 (0x3DF)
|
|
uint32_t reserved_992; // offset: 992 (0x3E0)
|
|
uint32_t reserved_993; // offset: 993 (0x3E1)
|
|
uint32_t reserved_994; // offset: 994 (0x3E2)
|
|
uint32_t reserved_995; // offset: 995 (0x3E3)
|
|
uint32_t reserved_996; // offset: 996 (0x3E4)
|
|
uint32_t reserved_997; // offset: 997 (0x3E5)
|
|
uint32_t reserved_998; // offset: 998 (0x3E6)
|
|
uint32_t reserved_999; // offset: 999 (0x3E7)
|
|
uint32_t reserved_1000; // offset: 1000 (0x3E8)
|
|
uint32_t reserved_1001; // offset: 1001 (0x3E9)
|
|
uint32_t reserved_1002; // offset: 1002 (0x3EA)
|
|
uint32_t reserved_1003; // offset: 1003 (0x3EB)
|
|
uint32_t reserved_1004; // offset: 1004 (0x3EC)
|
|
uint32_t reserved_1005; // offset: 1005 (0x3ED)
|
|
uint32_t reserved_1006; // offset: 1006 (0x3EE)
|
|
uint32_t reserved_1007; // offset: 1007 (0x3EF)
|
|
uint32_t reserved_1008; // offset: 1008 (0x3F0)
|
|
uint32_t reserved_1009; // offset: 1009 (0x3F1)
|
|
uint32_t reserved_1010; // offset: 1010 (0x3F2)
|
|
uint32_t reserved_1011; // offset: 1011 (0x3F3)
|
|
uint32_t reserved_1012; // offset: 1012 (0x3F4)
|
|
uint32_t reserved_1013; // offset: 1013 (0x3F5)
|
|
uint32_t reserved_1014; // offset: 1014 (0x3F6)
|
|
uint32_t reserved_1015; // offset: 1015 (0x3F7)
|
|
uint32_t reserved_1016; // offset: 1016 (0x3F8)
|
|
uint32_t reserved_1017; // offset: 1017 (0x3F9)
|
|
uint32_t reserved_1018; // offset: 1018 (0x3FA)
|
|
uint32_t reserved_1019; // offset: 1019 (0x3FB)
|
|
uint32_t reserved_1020; // offset: 1020 (0x3FC)
|
|
uint32_t reserved_1021; // offset: 1021 (0x3FD)
|
|
uint32_t reserved_1022; // offset: 1022 (0x3FE)
|
|
uint32_t reserved_1023; // offset: 1023 (0x3FF)
|
|
};
|
|
|
|
#endif /* V11_STRUCTS_H_ */
|