mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-04-14 09:57:39 +02:00
63fbf275fa
Add support for normalized CXL address translation through ACPI PRM method to support AMD Zen5 platforms. Including a conventions doc that explains how the translation is implemented and for future implementations that need such setup to comply with the current implementation method. cxl: Disable HPA/SPA translation handlers for Normalized Addressing cxl/region: Factor out code into cxl_region_setup_poison() cxl/atl: Lock decoders that need address translation cxl: Enable AMD Zen5 address translation using ACPI PRMT cxl/acpi: Prepare use of EFI runtime services cxl: Introduce callback for HPA address ranges translation cxl/region: Use region data to get the root decoder cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() cxl/region: Separate region parameter setup and region construction cxl: Simplify cxl_root_ops allocation and handling cxl/region: Store HPA range in struct cxl_region cxl/region: Store root decoder in struct cxl_region cxl/region: Rename misleading variable name @hpa to @hpa_range Documentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement cxl, doc: Moving conventions in separate files cxl, doc: Remove isonum.txt inclusion
76 lines
2.3 KiB
Makefile
76 lines
2.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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ldflags-y += --wrap=acpi_table_parse_cedt
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ldflags-y += --wrap=is_acpi_device_node
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ldflags-y += --wrap=acpi_evaluate_integer
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ldflags-y += --wrap=acpi_pci_find_root
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ldflags-y += --wrap=nvdimm_bus_register
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ldflags-y += --wrap=cxl_await_media_ready
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ldflags-y += --wrap=devm_cxl_add_rch_dport
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ldflags-y += --wrap=cxl_endpoint_parse_cdat
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ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
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ldflags-y += --wrap=hmat_get_extended_linear_cache_size
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ldflags-y += --wrap=devm_cxl_add_dport_by_dev
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ldflags-y += --wrap=devm_cxl_switch_port_decoders_setup
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DRIVERS := ../../../drivers
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CXL_SRC := $(DRIVERS)/cxl
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CXL_CORE_SRC := $(DRIVERS)/cxl/core
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ccflags-y := -I$(srctree)/drivers/cxl/
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ccflags-y += -D__mock=__weak
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ccflags-y += -DCXL_TEST_ENABLE=1
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ccflags-y += -DTRACE_INCLUDE_PATH=$(CXL_CORE_SRC) -I$(srctree)/drivers/cxl/core/
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obj-m += cxl_acpi.o
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cxl_acpi-y := $(CXL_SRC)/acpi.o
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cxl_acpi-y += mock_acpi.o
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cxl_acpi-y += config_check.o
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cxl_acpi-y += cxl_acpi_test.o
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obj-m += cxl_pmem.o
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cxl_pmem-y := $(CXL_SRC)/pmem.o
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cxl_pmem-y += $(CXL_SRC)/security.o
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cxl_pmem-y += config_check.o
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cxl_pmem-y += cxl_pmem_test.o
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obj-m += cxl_port.o
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cxl_port-y := $(CXL_SRC)/port.o
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cxl_port-y += config_check.o
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cxl_port-y += cxl_port_test.o
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obj-m += cxl_mem.o
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cxl_mem-y := $(CXL_SRC)/mem.o
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cxl_mem-y += config_check.o
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cxl_mem-y += cxl_mem_test.o
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obj-m += cxl_core.o
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cxl_core-y := $(CXL_CORE_SRC)/port.o
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cxl_core-y += $(CXL_CORE_SRC)/pmem.o
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cxl_core-y += $(CXL_CORE_SRC)/regs.o
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cxl_core-y += $(CXL_CORE_SRC)/memdev.o
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cxl_core-y += $(CXL_CORE_SRC)/mbox.o
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cxl_core-y += $(CXL_CORE_SRC)/pci.o
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cxl_core-y += $(CXL_CORE_SRC)/hdm.o
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cxl_core-y += $(CXL_CORE_SRC)/pmu.o
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cxl_core-y += $(CXL_CORE_SRC)/cdat.o
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cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
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cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
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cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o
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cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o
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cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += $(CXL_CORE_SRC)/edac.o
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cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras.o
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cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras_rch.o
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cxl_core-$(CONFIG_CXL_ATL) += $(CXL_CORE_SRC)/atl.o
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cxl_core-y += config_check.o
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cxl_core-y += cxl_core_test.o
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cxl_core-y += cxl_core_exports.o
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KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS))
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obj-m += test/
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