Biju Das 28548f3f79 clk: renesas: r9a09g047: Add XSPI clock/reset ...

Add XSPI clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

2025-05-08 20:17:55 +02:00

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clk-div6.c

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clk-div6.h

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clk-emev2.c

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clk-mstp.c

clk: Use of_property_present()

2024-08-02 16:53:38 -07:00

clk-r8a73a4.c

clk: renesas: Remove duplicate and trailing empty lines

2024-10-01 09:13:38 +02:00

clk-r8a7740.c

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clk-r8a7778.c

clk: renesas: Remove duplicate and trailing empty lines

2024-10-01 09:13:38 +02:00

clk-r8a7779.c

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clk-rz.c

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clk-sh73a0.c

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clk-vbattb.c

clk: renesas: vbattb: Add VBATTB clock driver

2024-11-06 08:52:45 +01:00

Kconfig

clk: renesas: rzv2h: Add support for RZ/V2N SoC

2025-04-14 10:58:14 +02:00

Makefile

clk: renesas: rzv2h: Add support for RZ/V2N SoC

2025-04-14 10:58:14 +02:00

r7s9210-cpg-mssr.c

clk: renesas: r7s9210: Distinguish clocks by clock type

2025-03-04 09:04:23 +01:00

r8a774a1-cpg-mssr.c

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r8a774b1-cpg-mssr.c

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r8a774c0-cpg-mssr.c

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r8a774e1-cpg-mssr.c

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r8a779a0-cpg-mssr.c

clk: renesas: r8a779a0: Add ISP core clocks

2025-02-03 11:07:05 +01:00

r8a779f0-cpg-mssr.c

clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs

2024-07-30 10:44:19 +02:00

r8a779g0-cpg-mssr.c

clk: renesas: r8a779g0: Add ISP core clocks

2025-02-03 11:07:05 +01:00

r8a779h0-cpg-mssr.c

clk: renesas: r8a779h0: Add VSPX clock

2025-02-03 11:07:06 +01:00

r8a7742-cpg-mssr.c

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r8a7743-cpg-mssr.c

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r8a7745-cpg-mssr.c

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r8a7790-cpg-mssr.c

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r8a7791-cpg-mssr.c

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r8a7792-cpg-mssr.c

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r8a7794-cpg-mssr.c

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r8a7795-cpg-mssr.c

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r8a7796-cpg-mssr.c

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r8a77470-cpg-mssr.c

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r8a77965-cpg-mssr.c

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r8a77970-cpg-mssr.c

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r8a77980-cpg-mssr.c

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r8a77990-cpg-mssr.c

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r8a77995-cpg-mssr.c

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r9a06g032-clocks.c

clk: renesas: r9a06g032: Use BIT macro consistently

2024-12-10 12:00:30 +01:00

r9a07g043-cpg.c

clk: renesas: r9a07g043: Fix HP clock source for RZ/Five

2025-02-03 11:07:06 +01:00

r9a07g044-cpg.c

clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI

2025-02-03 11:07:05 +01:00

r9a08g045-cpg.c

clk: renesas: r8a08g045: Check the source of the CPU PLL settings

2025-02-03 11:07:06 +01:00

r9a09g011-cpg.c

clk: renesas: Remove duplicate and trailing empty lines

2024-10-01 09:13:38 +02:00

r9a09g047-cpg.c

clk: renesas: r9a09g047: Add XSPI clock/reset

2025-05-08 20:17:55 +02:00

r9a09g056-cpg.c

clk: renesas: rzv2h: Add support for RZ/V2N SoC

2025-04-14 10:58:14 +02:00

r9a09g057-cpg.c

clk: renesas: r9a09g057: Add clock and reset entries for USB2

2025-04-22 11:38:28 +02:00

rcar-cpg-lib.c

clk: renesas: Remove duplicate and trailing empty lines

2024-10-01 09:13:38 +02:00

rcar-cpg-lib.h

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rcar-gen2-cpg.c

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rcar-gen2-cpg.h

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rcar-gen3-cpg.c

clk: renesas: Remove duplicate and trailing empty lines

2024-10-01 09:13:38 +02:00

rcar-gen3-cpg.h

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rcar-gen4-cpg.c

clk: renesas: rcar-gen4: Remove unused fixed PLL clock types

2024-07-30 10:44:19 +02:00

rcar-gen4-cpg.h

clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs

2024-07-30 10:44:19 +02:00

rcar-usb2-clock-sel.c

clk: Switch back to struct platform_driver::remove()

2024-09-21 14:12:05 -07:00

renesas-cpg-mssr.c

clk: renesas: Use str_on_off() helper

2025-05-05 10:48:07 +02:00

renesas-cpg-mssr.h

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rzg2l-cpg.c

clk: renesas: Use str_on_off() helper

2025-05-05 10:48:07 +02:00

rzg2l-cpg.h

clk: renesas: r8a08g045: Check the source of the CPU PLL settings

2025-02-03 11:07:06 +01:00

rzv2h-cpg.c

clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation

2025-04-22 11:27:12 +02:00

rzv2h-cpg.h

clk: renesas: r9a09g047: Add support for xspi mux and divider

2025-05-08 20:17:55 +02:00