mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-09 06:14:34 +02:00
Dmitry BaryshkovandBjorn Andersson
b2571ef8d4
Currently the database stores macrotile_mode in the data. However it can be derived from the rest of the data: it should be used for UBWC encoding >= 3.0 except for several corner cases (SM8150 and SC8180X). The ubwc_bank_spread field seems to be based on the impreside data we had for the MDSS and DPU programming. In some cases UBWC engine inside the display controller doesn't need to program it, although bank spread is to be enabled. Bank swizzle is also currently stored as is, but it is almost standard (banks 1-3 for UBWC 1.0 and 2-3 for other versions), the only exception being Lemans (it uses only bank 3). Add helpers returning values from the config for now. They will be rewritten later, in a separate series, but having the helper now simplifies refacroring the code later. Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260125-iris-ubwc-v4-2-1ff30644ac81@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018, The Linux Foundation
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef __QCOM_UBWC_H__
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#define __QCOM_UBWC_H__
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#include <linux/bits.h>
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#include <linux/printk.h>
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#include <linux/types.h>
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struct qcom_ubwc_cfg_data {
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u32 ubwc_enc_version;
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/* Can be read from MDSS_BASE + 0x58 */
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u32 ubwc_dec_version;
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/**
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* @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
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*
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* UBWC 1.0 always enables all three levels.
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* UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
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* UBWC 4.0 adds the optional ability to disable levels 2 & 3.
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*/
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u32 ubwc_swizzle;
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#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
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#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
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#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
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/**
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* @highest_bank_bit: Highest Bank Bit
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*
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* The Highest Bank Bit value represents the bit of the highest
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* DDR bank. This should ideally use DRAM type detection.
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*/
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int highest_bank_bit;
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bool ubwc_bank_spread;
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/**
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* @macrotile_mode: Macrotile Mode
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*
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* Whether to use 4-channel macrotiling mode or the newer
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* 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
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* 4-channel and 1 is 8-channel.
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*/
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bool macrotile_mode;
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};
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#define UBWC_1_0 0x10000000
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#define UBWC_2_0 0x20000000
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#define UBWC_3_0 0x30000000
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#define UBWC_4_0 0x40000000
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#define UBWC_4_3 0x40030000
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#define UBWC_5_0 0x50000000
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#define UBWC_6_0 0x60000000
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#if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG)
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const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
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#else
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static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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#endif
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static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
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{
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bool ret = cfg->ubwc_enc_version == UBWC_1_0;
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if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1))
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pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");
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return ret;
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}
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/*
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* This is the best guess, based on the MDSS driver, which worked so far.
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*/
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static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg)
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{
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return cfg->ubwc_enc_version == UBWC_1_0 &&
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(cfg->ubwc_dec_version == UBWC_2_0 ||
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cfg->ubwc_dec_version == UBWC_3_0);
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}
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static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg)
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{
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return cfg->macrotile_mode;
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}
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static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg)
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{
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return cfg->ubwc_bank_spread;
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}
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static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg)
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{
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return cfg->ubwc_swizzle;
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}
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#endif /* __QCOM_UBWC_H__ */
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