Thomas Gleixner 4b7de6df20 rseq: Cache CPU ID and MM CID values ...

In preparation for rewriting RSEQ exit to user space handling provide
storage to cache the CPU ID and MM CID values which were written to user
space. That prepares for a quick check, which avoids the update when
nothing changed.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://patch.msgid.link/20251027084306.841964081@linutronix.de

2025-11-04 08:32:14 +01:00

..

events

rseq: Cache CPU ID and MM CID values

2025-11-04 08:32:14 +01:00

misc

NFSD: filecache: add STATX_DIOALIGN and STATX_DIO_READ_ALIGN support

2025-09-30 16:10:05 -04:00

stages

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bpf_probe.h

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define_custom_trace.h

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define_trace.h

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perf.h

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syscall.h

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trace_custom_events.h

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trace_events.h

…