Laxman Dewangan 527fad1bc5 clk: tegra: initialise parent of uart clocks ...

Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

2013-02-13 11:17:03 -07:00

..

clk-audio-sync.c

…

clk-divider.c

…

clk-periph-gate.c

…

clk-periph.c

ARM: tegra: migrate to new clock code

2013-01-28 11:19:07 -07:00

clk-pll-out.c

…

clk-pll.c

…

clk-super.c

clk: tegra: Implement locking for super clock

2013-02-12 10:29:12 -07:00

clk-tegra20.c

clk: tegra: initialise parent of uart clocks

2013-02-13 11:17:03 -07:00

clk-tegra30.c

clk: tegra: initialise parent of uart clocks

2013-02-13 11:17:03 -07:00

clk.c

ARM: tegra: migrate to new clock code

2013-01-28 11:19:07 -07:00

clk.h

clk: tegra: add clock support for Tegra30

2013-01-28 11:19:07 -07:00

Makefile

clk: tegra: add clock support for Tegra30

2013-01-28 11:19:07 -07:00