Sebastien Van Cauwenberghe eefb5f3ab2 riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX ...

Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.

Signed-off-by: Sebastien Van Cauwenberghe <svancau@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

2021-02-02 18:36:29 -08:00

..

asm

riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX

2021-02-02 18:36:29 -08:00

uapi/asm

riscv: Add cache information in AUX vector

2020-09-15 18:46:08 -07:00