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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Matthew Auld
27cb2b7fec
This involves enabling l2 caching of host side memory access to VRAM
through the CPU BAR. The main fallout here is with display since VRAM
writes from CPU can now be cached in GPU l2, and display is never
coherent with caches, so needs various manual flushing. In the case of
fbc we disable it due to complications in getting this to work
correctly (in a later patch).
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240703124338.208220-3-matthew.auld@intel.com
(cherry picked from commit 01570b4469)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright 2023, Intel Corporation.
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*/
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#include "i915_vma.h"
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#include "intel_display_types.h"
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#include "intel_dsb_buffer.h"
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#include "xe_bo.h"
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#include "xe_device.h"
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#include "xe_device_types.h"
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#include "xe_gt.h"
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u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
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{
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return xe_bo_ggtt_addr(dsb_buf->vma->bo);
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}
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void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
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{
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struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
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iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
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xe_device_l2_flush(xe);
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}
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u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
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{
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return iosys_map_rd(&dsb_buf->vma->bo->vmap, idx * 4, u32);
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}
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void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
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{
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struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
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WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
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iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
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xe_device_l2_flush(xe);
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}
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bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
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{
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struct xe_device *xe = to_xe_device(crtc->base.dev);
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struct xe_bo *obj;
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struct i915_vma *vma;
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vma = kzalloc(sizeof(*vma), GFP_KERNEL);
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if (!vma)
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return false;
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obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
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NULL, PAGE_ALIGN(size),
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ttm_bo_type_kernel,
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XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
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XE_BO_FLAG_GGTT);
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if (IS_ERR(obj)) {
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kfree(vma);
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return false;
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}
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vma->bo = obj;
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dsb_buf->vma = vma;
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dsb_buf->buf_size = size;
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return true;
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}
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void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
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{
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xe_bo_unpin_map_no_vm(dsb_buf->vma->bo);
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kfree(dsb_buf->vma);
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}
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void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
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{
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/* TODO: add xe specific flush_map() for dsb buffer object. */
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}
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