Gustavo Sousa 968290fa8a drm/i915/cdclk: Implement Wa_13012396614 ...

A new workaround was defined for Xe3_LPD, which requires a tweak on how
we handle MDCLK selection.  Implement it.

Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patch.msgid.link/20251222-display-wa-13012396614-timing-of-mdclk-source-selection-v1-2-a2f7e9447f7a@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

2026-01-05 16:44:26 -03:00

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drm

drm/i915/cdclk: Implement Wa_13012396614

2026-01-05 16:44:26 -03:00

host1x

gpu: host1x: Syncpoint interrupt performance optimization

2025-11-14 18:27:19 +01:00

ipu-v3

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nova-core

Merge tag 'driver-core-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core

2025-12-05 21:29:02 -08:00

trace

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vga

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Makefile

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