Pauli Nieminen 9e5b2af75a drm/r100/kms: Emit cache flush to the end of command buffer. (v2) ...

Cache flush is required in case CPU is accessing rendered data.

This fixes glean/readPixSanity test case and random rendering
errors in sauerbraten and warzone2100.

v2 Fix comment ordering in r100_fence_ring_emit and remove extra
   defines added in first version.

Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

2010-02-05 11:45:10 +10:00

..

drm

drm/r100/kms: Emit cache flush to the end of command buffer. (v2)

2010-02-05 11:45:10 +10:00

vga

PCI/vgaarb: cleanup some warnings + cleanup some comments.

2009-09-09 13:29:41 -07:00

Makefile

PCI/GPU: implement VGA arbitration on Linux

2009-09-09 13:29:36 -07:00