mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-06-21 15:43:21 +02:00
Shay Drory
d6c9b4de81
Downstream patches will introduce SW-only LAG (e.g. shared_fdb without HW LAG). In this mode the firmware cannot create the LAG demux table, but vport demuxing is still required. Move LAG demux flow-table ownership to the LAG layer and introduce APIs to init/cleanup the demux table and add/delete per-vport rules. Adjust the RDMA driver to use the new APIs. In this mode, the LAG layer will create a flow group that matches vport metadata. Vports that are not native to the LAG master eswitch add the demux rule during IB representor load and remove it on unload. The demux rule forward traffic from said vports to their native eswitch manager via a new dest type - MLX5_FLOW_DESTINATION_TYPE_VHCA_RX. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260309093435.1850724-9-tariqt@nvidia.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
386 lines
11 KiB
C
386 lines
11 KiB
C
/*
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* Copyright (c) 2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _MLX5_FS_
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#define _MLX5_FS_
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/mlx5_ifc.h>
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#define MLX5_FS_DEFAULT_FLOW_TAG 0x0
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#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
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#define MLX5_RDMA_TRANSPORT_BYPASS_PRIO 16
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#define MLX5_FS_MAX_POOL_SIZE BIT(30)
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enum mlx5_flow_destination_type {
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MLX5_FLOW_DESTINATION_TYPE_NONE,
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MLX5_FLOW_DESTINATION_TYPE_VPORT,
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MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE,
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MLX5_FLOW_DESTINATION_TYPE_TIR,
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MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER,
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MLX5_FLOW_DESTINATION_TYPE_UPLINK,
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MLX5_FLOW_DESTINATION_TYPE_PORT,
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MLX5_FLOW_DESTINATION_TYPE_COUNTER,
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MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM,
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MLX5_FLOW_DESTINATION_TYPE_RANGE,
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MLX5_FLOW_DESTINATION_TYPE_TABLE_TYPE,
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MLX5_FLOW_DESTINATION_TYPE_VHCA_RX,
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};
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enum {
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MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 1 << 16,
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MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 17,
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MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 1 << 18,
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MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS = 1 << 19,
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};
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enum {
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MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),
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MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
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MLX5_FLOW_TABLE_TERMINATION = BIT(2),
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MLX5_FLOW_TABLE_UNMANAGED = BIT(3),
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MLX5_FLOW_TABLE_OTHER_VPORT = BIT(4),
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MLX5_FLOW_TABLE_UPLINK_VPORT = BIT(5),
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MLX5_FLOW_TABLE_OTHER_ESWITCH = BIT(6),
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};
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#define LEFTOVERS_RULE_NUM 2
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static inline void build_leftovers_ft_param(int *priority,
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int *n_ent,
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int *n_grp)
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{
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*priority = 0; /* Priority of leftovers_prio-0 */
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*n_ent = LEFTOVERS_RULE_NUM;
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*n_grp = LEFTOVERS_RULE_NUM;
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}
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enum mlx5_flow_namespace_type {
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MLX5_FLOW_NAMESPACE_BYPASS,
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MLX5_FLOW_NAMESPACE_KERNEL_RX_MACSEC,
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MLX5_FLOW_NAMESPACE_LAG,
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MLX5_FLOW_NAMESPACE_OFFLOADS,
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MLX5_FLOW_NAMESPACE_ETHTOOL,
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MLX5_FLOW_NAMESPACE_KERNEL,
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MLX5_FLOW_NAMESPACE_LEFTOVERS,
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MLX5_FLOW_NAMESPACE_ANCHOR,
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MLX5_FLOW_NAMESPACE_FDB_BYPASS,
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MLX5_FLOW_NAMESPACE_FDB,
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MLX5_FLOW_NAMESPACE_ESW_EGRESS,
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MLX5_FLOW_NAMESPACE_ESW_INGRESS,
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MLX5_FLOW_NAMESPACE_SNIFFER_RX,
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MLX5_FLOW_NAMESPACE_SNIFFER_TX,
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MLX5_FLOW_NAMESPACE_EGRESS,
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MLX5_FLOW_NAMESPACE_EGRESS_IPSEC,
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MLX5_FLOW_NAMESPACE_EGRESS_MACSEC,
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MLX5_FLOW_NAMESPACE_RDMA_RX,
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MLX5_FLOW_NAMESPACE_RDMA_RX_KERNEL,
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MLX5_FLOW_NAMESPACE_RDMA_TX,
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MLX5_FLOW_NAMESPACE_PORT_SEL,
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MLX5_FLOW_NAMESPACE_RDMA_RX_COUNTERS,
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MLX5_FLOW_NAMESPACE_RDMA_TX_COUNTERS,
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MLX5_FLOW_NAMESPACE_RDMA_RX_IPSEC,
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MLX5_FLOW_NAMESPACE_RDMA_TX_IPSEC,
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MLX5_FLOW_NAMESPACE_RDMA_RX_MACSEC,
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MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC,
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MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_RX,
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MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_TX,
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};
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enum {
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FDB_DROP_ROOT,
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FDB_BYPASS_PATH,
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FDB_CRYPTO_INGRESS,
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FDB_TC_OFFLOAD,
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FDB_FT_OFFLOAD,
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FDB_TC_MISS,
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FDB_BR_OFFLOAD,
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FDB_SLOW_PATH,
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FDB_CRYPTO_EGRESS,
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FDB_PER_VPORT,
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};
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enum fs_flow_table_type {
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FS_FT_NIC_RX = 0x0,
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FS_FT_NIC_TX = 0x1,
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FS_FT_ESW_EGRESS_ACL = 0x2,
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FS_FT_ESW_INGRESS_ACL = 0x3,
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FS_FT_FDB = 0X4,
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FS_FT_SNIFFER_RX = 0X5,
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FS_FT_SNIFFER_TX = 0X6,
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FS_FT_RDMA_RX = 0X7,
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FS_FT_RDMA_TX = 0X8,
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FS_FT_PORT_SEL = 0X9,
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FS_FT_FDB_RX = 0xa,
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FS_FT_FDB_TX = 0xb,
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FS_FT_RDMA_TRANSPORT_RX = 0xd,
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FS_FT_RDMA_TRANSPORT_TX = 0xe,
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FS_FT_MAX_TYPE = FS_FT_RDMA_TRANSPORT_TX,
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};
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struct mlx5_pkt_reformat;
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struct mlx5_modify_hdr;
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struct mlx5_flow_definer;
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struct mlx5_flow_table;
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struct mlx5_flow_group;
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struct mlx5_flow_namespace;
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struct mlx5_flow_handle;
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enum {
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FLOW_CONTEXT_HAS_TAG = BIT(0),
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FLOW_CONTEXT_UPLINK_HAIRPIN_EN = BIT(1),
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};
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struct mlx5_flow_context {
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u32 flags;
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u32 flow_tag;
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u32 flow_source;
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};
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struct mlx5_flow_spec {
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u8 match_criteria_enable;
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u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
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u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
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struct mlx5_flow_context flow_context;
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};
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enum {
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MLX5_FLOW_DEST_VPORT_VHCA_ID = BIT(0),
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MLX5_FLOW_DEST_VPORT_REFORMAT_ID = BIT(1),
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};
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enum mlx5_flow_dest_range_field {
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MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN = 0,
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};
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struct mlx5_flow_destination {
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enum mlx5_flow_destination_type type;
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union {
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u32 tir_num;
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u32 ft_num;
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struct mlx5_flow_table *ft;
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struct mlx5_fc *counter;
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struct {
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u16 id;
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} vhca;
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struct {
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u16 num;
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u16 vhca_id;
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struct mlx5_pkt_reformat *pkt_reformat;
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u8 flags;
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} vport;
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struct {
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struct mlx5_flow_table *hit_ft;
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struct mlx5_flow_table *miss_ft;
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enum mlx5_flow_dest_range_field field;
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u32 min;
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u32 max;
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} range;
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u32 sampler_id;
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};
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};
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struct mod_hdr_tbl {
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struct mutex lock; /* protects hlist */
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DECLARE_HASHTABLE(hlist, 8);
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};
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struct mlx5_flow_namespace *
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mlx5_get_fdb_sub_ns(struct mlx5_core_dev *dev, int n);
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struct mlx5_flow_namespace *
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mlx5_get_flow_namespace(struct mlx5_core_dev *dev,
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enum mlx5_flow_namespace_type type);
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struct mlx5_flow_namespace *
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mlx5_get_flow_vport_namespace(struct mlx5_core_dev *dev,
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enum mlx5_flow_namespace_type type,
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int vport_idx);
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struct mlx5_flow_table_attr {
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int prio;
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int max_fte;
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u32 level;
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u32 flags;
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u16 uid;
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u16 vport;
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u16 esw_owner_vhca_id;
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struct mlx5_flow_table *next_ft;
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struct {
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int max_num_groups;
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int num_reserved_entries;
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} autogroup;
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};
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struct mlx5_flow_table *
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mlx5_create_flow_table(struct mlx5_flow_namespace *ns,
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struct mlx5_flow_table_attr *ft_attr);
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struct mlx5_flow_table *
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mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
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struct mlx5_flow_table_attr *ft_attr);
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struct mlx5_flow_table *
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mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
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struct mlx5_flow_table_attr *ft_attr, u16 vport);
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struct mlx5_flow_table *
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mlx5_create_lag_demux_flow_table(struct mlx5_flow_namespace *ns,
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struct mlx5_flow_table_attr *ft_attr);
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int mlx5_destroy_flow_table(struct mlx5_flow_table *ft);
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/* inbox should be set with the following values:
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* start_flow_index
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* end_flow_index
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* match_criteria_enable
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* match_criteria
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*/
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struct mlx5_flow_group *
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mlx5_create_flow_group(struct mlx5_flow_table *ft, u32 *in);
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void mlx5_destroy_flow_group(struct mlx5_flow_group *fg);
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struct mlx5_exe_aso {
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u32 object_id;
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int base_id;
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u8 type;
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u8 return_reg_id;
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union {
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u32 ctrl_data;
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struct {
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u8 meter_idx;
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u8 init_color;
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} flow_meter;
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};
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};
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struct mlx5_fs_vlan {
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u16 ethtype;
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u16 vid;
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u8 prio;
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};
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#define MLX5_FS_VLAN_DEPTH 2
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enum {
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FLOW_ACT_NO_APPEND = BIT(0),
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FLOW_ACT_IGNORE_FLOW_LEVEL = BIT(1),
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};
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struct mlx5_flow_act {
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u32 action;
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struct mlx5_modify_hdr *modify_hdr;
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struct mlx5_pkt_reformat *pkt_reformat;
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struct mlx5_flow_act_crypto_params {
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u8 type;
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u32 obj_id;
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} crypto;
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u32 flags;
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struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
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struct ib_counters *counters;
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struct mlx5_flow_group *fg;
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struct mlx5_exe_aso exe_aso;
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};
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#define MLX5_DECLARE_FLOW_ACT(name) \
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struct mlx5_flow_act name = { .action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,\
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.flags = 0, }
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/* Single destination per rule.
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* Group ID is implied by the match criteria.
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*/
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struct mlx5_flow_handle *
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mlx5_add_flow_rules(struct mlx5_flow_table *ft,
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const struct mlx5_flow_spec *spec,
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struct mlx5_flow_act *flow_act,
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struct mlx5_flow_destination *dest,
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int num_dest);
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void mlx5_del_flow_rules(struct mlx5_flow_handle *fr);
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int mlx5_modify_rule_destination(struct mlx5_flow_handle *handler,
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struct mlx5_flow_destination *new_dest,
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struct mlx5_flow_destination *old_dest);
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struct mlx5_fc *mlx5_fc_create(struct mlx5_core_dev *dev, bool aging);
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void mlx5_fc_destroy(struct mlx5_core_dev *dev, struct mlx5_fc *counter);
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struct mlx5_fc *mlx5_fc_local_create(u32 counter_id, u32 offset, u32 bulk_size);
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void mlx5_fc_local_destroy(struct mlx5_fc *counter);
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void mlx5_fc_local_get(struct mlx5_fc *counter);
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void mlx5_fc_local_put(struct mlx5_fc *counter);
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u64 mlx5_fc_query_lastuse(struct mlx5_fc *counter);
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void mlx5_fc_query_cached(struct mlx5_fc *counter,
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u64 *bytes, u64 *packets, u64 *lastuse);
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void mlx5_fc_query_cached_raw(struct mlx5_fc *counter,
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u64 *bytes, u64 *packets, u64 *lastuse);
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int mlx5_fc_query(struct mlx5_core_dev *dev, struct mlx5_fc *counter,
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u64 *packets, u64 *bytes);
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u32 mlx5_fc_id(struct mlx5_fc *counter);
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int mlx5_fs_add_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);
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int mlx5_fs_remove_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);
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struct mlx5_modify_hdr *mlx5_modify_header_alloc(struct mlx5_core_dev *dev,
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u8 ns_type, u8 num_actions,
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void *modify_actions);
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void mlx5_modify_header_dealloc(struct mlx5_core_dev *dev,
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struct mlx5_modify_hdr *modify_hdr);
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struct mlx5_flow_definer *
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mlx5_create_match_definer(struct mlx5_core_dev *dev,
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enum mlx5_flow_namespace_type ns_type, u16 format_id,
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u32 *match_mask);
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void mlx5_destroy_match_definer(struct mlx5_core_dev *dev,
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struct mlx5_flow_definer *definer);
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int mlx5_get_match_definer_id(struct mlx5_flow_definer *definer);
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struct mlx5_pkt_reformat_params {
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int type;
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u8 param_0;
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u8 param_1;
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size_t size;
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void *data;
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};
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struct mlx5_pkt_reformat *mlx5_packet_reformat_alloc(struct mlx5_core_dev *dev,
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struct mlx5_pkt_reformat_params *params,
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enum mlx5_flow_namespace_type ns_type);
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void mlx5_packet_reformat_dealloc(struct mlx5_core_dev *dev,
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struct mlx5_pkt_reformat *reformat);
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u32 mlx5_flow_table_id(struct mlx5_flow_table *ft);
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struct mlx5_flow_root_namespace *
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mlx5_get_root_namespace(struct mlx5_core_dev *dev, enum mlx5_flow_namespace_type ns_type);
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int mlx5_fs_set_root_dev(struct mlx5_core_dev *dev,
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struct mlx5_core_dev *new_dev,
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enum fs_flow_table_type table_type);
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#endif
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