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linux-stable-mirror/include/linux/pci-epc.h
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Manikanta Maddireddy 5f352433ea PCI: endpoint: Add reserved region type for MSI-X Table and PBA 
Add PCI_EPC_BAR_RSVD_MSIX_TBL_RAM and PCI_EPC_BAR_RSVD_MSIX_PBA_RAM to
enum pci_epc_bar_rsvd_region_type so that Endpoint controllers can
describe hardware-owned MSI-X Table and PBA (Pending Bit Array) regions
behind a BAR_RESERVED BAR.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://patch.msgid.link/20260324080857.916263-2-mmaddireddy@nvidia.com
2026-04-04 16:14:37 +05:30

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* PCI Endpoint *Controller* (EPC) header file
*
* Copyright (C) 2017 Texas Instruments
* Author: Kishon Vijay Abraham I <kishon@ti.com>
*/
#ifndef __LINUX_PCI_EPC_H
#define __LINUX_PCI_EPC_H
#include <linux/pci-epf.h>
struct pci_epc;
enum pci_epc_interface_type {
UNKNOWN_INTERFACE = -1,
PRIMARY_INTERFACE,
SECONDARY_INTERFACE,
};
static inline const char *
pci_epc_interface_string(enum pci_epc_interface_type type)
{
switch (type) {
case PRIMARY_INTERFACE:
return "primary";
case SECONDARY_INTERFACE:
return "secondary";
default:
return "UNKNOWN interface";
}
}
/**
* struct pci_epc_map - information about EPC memory for mapping a RC PCI
* address range
* @pci_addr: start address of the RC PCI address range to map
* @pci_size: size of the RC PCI address range mapped from @pci_addr
* @map_pci_addr: RC PCI address used as the first address mapped (may be lower
* than @pci_addr)
* @map_size: size of the controller memory needed for mapping the RC PCI address
* range @map_pci_addr..@pci_addr+@pci_size
* @phys_base: base physical address of the allocated EPC memory for mapping the
* RC PCI address range
* @phys_addr: physical address at which @pci_addr is mapped
* @virt_base: base virtual address of the allocated EPC memory for mapping the
* RC PCI address range
* @virt_addr: virtual address at which @pci_addr is mapped
*/
struct pci_epc_map {
u64 pci_addr;
size_t pci_size;
u64 map_pci_addr;
size_t map_size;
phys_addr_t phys_base;
phys_addr_t phys_addr;
void __iomem *virt_base;
void __iomem *virt_addr;
};
/**
* struct pci_epc_ops - set of function pointers for performing EPC operations
* @write_header: ops to populate configuration space header
* @set_bar: ops to configure the BAR
* @clear_bar: ops to reset the BAR
* @align_addr: operation to get the mapping address, mapping size and offset
* into a controller memory window needed to map an RC PCI address
* region
* @map_addr: ops to map CPU address to PCI address
* @unmap_addr: ops to unmap CPU address and PCI address
* @set_msi: ops to set the requested number of MSI interrupts in the MSI
* capability register
* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
* the MSI capability register
* @set_msix: ops to set the requested number of MSI-X interrupts in the
* MSI-X capability register
* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
* from the MSI-X capability register
* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
* @map_msi_irq: ops to map physical address to MSI address and return MSI data
* @start: ops to start the PCI link
* @stop: ops to stop the PCI link
* @get_features: ops to get the features supported by the EPC
* @owner: the module owner containing the ops
*/
struct pci_epc_ops {
int (*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epf_header *hdr);
int (*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epf_bar *epf_bar);
void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epf_bar *epf_bar);
u64 (*align_addr)(struct pci_epc *epc, u64 pci_addr, size_t *size,
size_t *offset);
int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t addr, u64 pci_addr, size_t size);
void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t addr);
int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
u8 nr_irqs);
int (*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int (*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
u16 nr_irqs, enum pci_barno, u32 offset);
int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
unsigned int type, u16 interrupt_num);
int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t phys_addr, u8 interrupt_num,
u32 entry_size, u32 *msi_data,
u32 *msi_addr_offset);
int (*start)(struct pci_epc *epc);
void (*stop)(struct pci_epc *epc);
const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
u8 func_no, u8 vfunc_no);
struct module *owner;
};
/**
* struct pci_epc_mem_window - address window of the endpoint controller
* @phys_base: physical base address of the PCI address window
* @size: the size of the PCI address window
* @page_size: size of each page
*/
struct pci_epc_mem_window {
phys_addr_t phys_base;
size_t size;
size_t page_size;
};
/**
* struct pci_epc_mem - address space of the endpoint controller
* @window: address window of the endpoint controller
* @bitmap: bitmap to manage the PCI address space
* @pages: number of bits representing the address region
* @lock: mutex to protect bitmap
*/
struct pci_epc_mem {
struct pci_epc_mem_window window;
unsigned long *bitmap;
int pages;
/* mutex to protect against concurrent access for memory allocation*/
struct mutex lock;
};
/**
* struct pci_epc - represents the PCI EPC device
* @dev: PCI EPC device
* @pci_epf: list of endpoint functions present in this EPC device
* @list_lock: Mutex for protecting pci_epf list
* @ops: function pointers for performing endpoint operations
* @windows: array of address space of the endpoint controller
* @mem: first window of the endpoint controller, which corresponds to
* default address space of the endpoint controller supporting
* single window.
* @num_windows: number of windows supported by device
* @max_functions: max number of functions that can be configured in this EPC
* @max_vfs: Array indicating the maximum number of virtual functions that can
* be associated with each physical function
* @group: configfs group representing the PCI EPC device
* @lock: mutex to protect pci_epc ops
* @function_num_map: bitmap to manage physical function number
* @domain_nr: PCI domain number of the endpoint controller
* @init_complete: flag to indicate whether the EPC initialization is complete
* or not
*/
struct pci_epc {
struct device dev;
struct list_head pci_epf;
struct mutex list_lock;
const struct pci_epc_ops *ops;
struct pci_epc_mem **windows;
struct pci_epc_mem *mem;
unsigned int num_windows;
u8 max_functions;
u8 *max_vfs;
struct config_group *group;
/* mutex to protect against concurrent access of EP controller */
struct mutex lock;
unsigned long function_num_map;
int domain_nr;
bool init_complete;
};
/**
* enum pci_epc_bar_type - configurability of endpoint BAR
* @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
* @BAR_FIXED: The BAR mask is fixed by the hardware.
* @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
* NOTE: An EPC driver can currently only set a single supported
* size.
* @BAR_RESERVED: Used for HW-backed BARs (e.g. MSI-X table, DMA regs). The BAR
* should not be disabled by an EPC driver. The BAR should not be
* reprogrammed by an EPF driver. An EPF driver is allowed to
* disable the BAR if absolutely necessary. (However, right now
* there is no EPC operation to disable a BAR that has not been
* programmed using pci_epc_set_bar().)
* @BAR_DISABLED: The BAR should be disabled by an EPC driver. The BAR will be
* unavailable to an EPF driver.
*/
enum pci_epc_bar_type {
BAR_PROGRAMMABLE = 0,
BAR_FIXED,
BAR_RESIZABLE,
BAR_RESERVED,
BAR_DISABLED,
};
/**
* enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
* @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
* @PCI_EPC_BAR_RSVD_MSIX_TBL_RAM: MSI-X table structure
* @PCI_EPC_BAR_RSVD_MSIX_PBA_RAM: MSI-X PBA structure
*
* BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
* reprogrammed by EPF drivers. Some of them still expose fixed subregions that
* EPFs may want to reference (e.g. embedded doorbell fallback).
*/
enum pci_epc_bar_rsvd_region_type {
PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
PCI_EPC_BAR_RSVD_MSIX_TBL_RAM,
PCI_EPC_BAR_RSVD_MSIX_PBA_RAM,
};
/**
* struct pci_epc_bar_rsvd_region - fixed subregion behind a BAR
* @type: reserved region type
* @offset: offset within the BAR aperture
* @size: size of the reserved region
*/
struct pci_epc_bar_rsvd_region {
enum pci_epc_bar_rsvd_region_type type;
resource_size_t offset;
resource_size_t size;
};
/**
* struct pci_epc_bar_desc - hardware description for a BAR
* @type: the type of the BAR
* @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
* @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
* should be configured as 32-bit or 64-bit, the EPF driver must
* configure this BAR as 64-bit.
* @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
* @rsvd_regions: fixed subregions behind BAR_RESERVED
*/
struct pci_epc_bar_desc {
enum pci_epc_bar_type type;
u64 fixed_size;
bool only_64bit;
u8 nr_rsvd_regions;
const struct pci_epc_bar_rsvd_region *rsvd_regions;
};
/**
* struct pci_epc_features - features supported by a EPC device per function
* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
* @dynamic_inbound_mapping: indicate if the EPC device supports updating
* inbound mappings for an already configured BAR
* (i.e. allow calling pci_epc_set_bar() again
* without first calling pci_epc_clear_bar())
* @subrange_mapping: indicate if the EPC device can map inbound subranges for a
* BAR. This feature depends on @dynamic_inbound_mapping
* feature.
* @msi_capable: indicate if the endpoint function has MSI capability
* @msix_capable: indicate if the endpoint function has MSI-X capability
* @intx_capable: indicate if the endpoint can raise INTx interrupts
* @bar: array specifying the hardware description for each BAR
* @align: alignment size required for BAR buffer allocation
*/
struct pci_epc_features {
unsigned int linkup_notifier : 1;
unsigned int dynamic_inbound_mapping : 1;
unsigned int subrange_mapping : 1;
unsigned int msi_capable : 1;
unsigned int msix_capable : 1;
unsigned int intx_capable : 1;
struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
size_t align;
};
#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
#ifdef CONFIG_PCI_ENDPOINT
#define pci_epc_create(dev, ops) \
__pci_epc_create((dev), (ops), THIS_MODULE)
#define devm_pci_epc_create(dev, ops) \
__devm_pci_epc_create((dev), (ops), THIS_MODULE)
static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
{
dev_set_drvdata(&epc->dev, data);
}
static inline void *epc_get_drvdata(struct pci_epc *epc)
{
return dev_get_drvdata(&epc->dev);
}
struct pci_epc *
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
struct module *owner);
struct pci_epc *
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
struct module *owner);
void pci_epc_destroy(struct pci_epc *epc);
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
enum pci_epc_interface_type type);
void pci_epc_linkup(struct pci_epc *epc);
void pci_epc_linkdown(struct pci_epc *epc);
void pci_epc_init_notify(struct pci_epc *epc);
void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf);
void pci_epc_deinit_notify(struct pci_epc *epc);
void pci_epc_bus_master_enable_notify(struct pci_epc *epc);
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
enum pci_epc_interface_type type);
int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epf_header *hdr);
int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap);
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epf_bar *epf_bar);
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epf_bar *epf_bar);
int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t phys_addr,
u64 pci_addr, size_t size);
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 nr_irqs);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u16 nr_irqs,
enum pci_barno, u32 offset);
int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t phys_addr, u8 interrupt_num,
u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
unsigned int type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
u8 func_no, u8 vfunc_no);
enum pci_barno
pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
*epc_features, enum pci_barno bar);
struct pci_epc *pci_epc_get(const char *epc_name);
void pci_epc_put(struct pci_epc *epc);
int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
size_t size, size_t page_size);
int pci_epc_multi_mem_init(struct pci_epc *epc,
struct pci_epc_mem_window *window,
unsigned int num_windows);
void pci_epc_mem_exit(struct pci_epc *epc);
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
phys_addr_t *phys_addr, size_t size);
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
void __iomem *virt_addr, size_t size);
int pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
u64 pci_addr, size_t pci_size, struct pci_epc_map *map);
void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
struct pci_epc_map *map);
#else
static inline void pci_epc_init_notify(struct pci_epc *epc)
{
}
static inline void pci_epc_deinit_notify(struct pci_epc *epc)
{
}
#endif /* CONFIG_PCI_ENDPOINT */
#endif /* __LINUX_PCI_EPC_H */
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