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Andy Shevchenko
fe364a7d95
Intel Elkhart Lake PSE DMA implementation is integrated with crossbar IP in order to serve more hardware than there are DMA request lines available. Due to this, program xBAR hardware to make flexible support of PSE peripheral. The Device-to-Device has not been tested and it's not supported by DMA Engine, but it's left in the code for the sake of documenting hardware features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210712113940.42753-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Driver for the Synopsys DesignWare DMA Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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*/
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#ifndef _PLATFORM_DATA_DMA_DW_H
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#define _PLATFORM_DATA_DMA_DW_H
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#include <linux/bits.h>
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#include <linux/types.h>
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#define DW_DMA_MAX_NR_MASTERS 4
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#define DW_DMA_MAX_NR_CHANNELS 8
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#define DW_DMA_MIN_BURST 1
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#define DW_DMA_MAX_BURST 256
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struct device;
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @src_id: src request line
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* @dst_id: dst request line
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* @m_master: memory master for transfers on allocated channel
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* @p_master: peripheral master for transfers on allocated channel
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* @channels: mask of the channels permitted for allocation (zero value means any)
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* @hs_polarity:set active low polarity of handshake interface
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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u8 src_id;
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u8 dst_id;
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u8 m_master;
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u8 p_master;
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u8 channels;
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bool hs_polarity;
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};
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @chan_allocation_order: Allocate channels starting from 0 or 7
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* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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* @block_size: Maximum block size supported by the controller
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* @nr_masters: Number of AHB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per AHB master
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* (in bytes, power of 2)
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* @multi_block: Multi block transfers supported by hardware per channel.
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* @max_burst: Maximum value of burst transaction size supported by hardware
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* per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
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* @protctl: Protection control signals setting per channel.
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* @quirks: Optional platform quirks.
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
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unsigned char chan_priority;
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unsigned int block_size;
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unsigned char nr_masters;
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unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
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unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
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u32 max_burst[DW_DMA_MAX_NR_CHANNELS];
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#define CHAN_PROTCTL_PRIVILEGED BIT(0)
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#define CHAN_PROTCTL_BUFFERABLE BIT(1)
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#define CHAN_PROTCTL_CACHEABLE BIT(2)
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#define CHAN_PROTCTL_MASK GENMASK(2, 0)
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unsigned char protctl;
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#define DW_DMA_QUIRK_XBAR_PRESENT BIT(0)
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unsigned int quirks;
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};
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#endif /* _PLATFORM_DATA_DMA_DW_H */
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