Sebastian Andrzej Siewior e3f21fdea4 perf/cxlpmu: Replace IRQF_ONESHOT with IRQF_NO_THREAD ...

[ Upstream commit ab26d9c855 ]

Passing IRQF_ONESHOT ensures that the interrupt source is masked until
the secondary (threaded) handler is done. If only a primary handler is
used then the flag makes no sense because the interrupt can not fire
(again) while its handler is running.
The flag also disallows force-threading of the primary handler and the
irq-core will warn about this.

The intention here was probably not allowing forced-threading.

Replace IRQF_ONESHOT with IRQF_NO_THREAD.

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2026-03-04 07:20:55 -05:00

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amlogic

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arm_cspmu

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hisilicon

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alibaba_uncore_drw_pmu.c

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apple_m1_cpu_pmu.c

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arm_dmc620_pmu.c

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arm_dsu_pmu.c

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arm_pmu_acpi.c

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arm_pmu_platform.c

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arm_pmu.c

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arm_pmuv3.c

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arm_smmuv3_pmu.c

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arm_spe_pmu.c

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arm_v6_pmu.c

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arm_v7_pmu.c

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arm_xscale_pmu.c

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arm-cci.c

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arm-ccn.c

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arm-cmn.c

perf/arm-cmn: Support CMN-600AE

2026-03-04 07:20:53 -05:00

arm-ni.c

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cxl_pmu.c

perf/cxlpmu: Replace IRQF_ONESHOT with IRQF_NO_THREAD

2026-03-04 07:20:55 -05:00

dwc_pcie_pmu.c

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fsl_imx8_ddr_perf.c

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fsl_imx9_ddr_perf.c

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Kconfig

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Makefile

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marvell_cn10k_ddr_pmu.c

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marvell_cn10k_tad_pmu.c

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qcom_l2_pmu.c

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qcom_l3_pmu.c

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riscv_pmu_legacy.c

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riscv_pmu_sbi.c

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riscv_pmu.c

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starfive_starlink_pmu.c

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thunderx2_pmu.c

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xgene_pmu.c

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