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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Djordje Todorovic
0b0ca959d2
Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs. Handle errata for the MIPS PAUSE instruction. Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com> Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-7-a6cbbe1c3412@htecgroup.com [pjw@kernel.org: updated to apply and compile; fixed a checkpatch issue] Signed-off-by: Paul Walmsley <pjw@kernel.org>
30 lines
592 B
C
30 lines
592 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_VDSO_PROCESSOR_H
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#define __ASM_VDSO_PROCESSOR_H
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#ifndef __ASSEMBLER__
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#include <asm/barrier.h>
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#include <asm/errata_list.h>
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#include <asm/insn-def.h>
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static inline void cpu_relax(void)
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{
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#ifdef __riscv_muldiv
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int dummy;
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/* In lieu of a halt instruction, induce a long-latency stall. */
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__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
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#endif
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/*
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* Reduce instruction retirement.
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* This assumes the PC changes.
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*/
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ALT_RISCV_PAUSE();
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barrier();
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}
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_VDSO_PROCESSOR_H */
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