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Chen Wang
1c72774df0
Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe controller in SG2042 works in host mode only, supporting data rate up to 16 GT/s and lanes up to x16 or x8. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [mani: reworded description and minor code cleanups] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com
8 lines
328 B
Makefile
8 lines
328 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
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obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
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obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
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obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
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obj-$(CONFIG_PCI_J721E) += pci-j721e.o
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obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o
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