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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-05-14 21:38:46 +02:00
Christian Bruel
151f3d29ba
Add driver to configure the STM32MP25 SoC PCIe controller based on the DesignWare PCIe core in endpoint mode. Controller support 2.5 and 5 GT/s data rates and uses the common reference clock provided by the host. The PCIe core_clk receives the pipe0_clk from the ComboPHY as input, and the ComboPHY PLL must be locked for pipe0_clk to be ready. Consequently, PCIe core registers cannot be accessed until the ComboPHY is fully initialised and REFCLK is enabled and ready. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> [mani: reworded description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: squash in https://patch.msgid.link/20250902122641.269725-1-christian.bruel@foss.st.com to remove redundant link_status checks] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250820075411.1178729-7-christian.bruel@foss.st.com
57 lines
2.3 KiB
Makefile
57 lines
2.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
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obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
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obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
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obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
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obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
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obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
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obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
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obj-$(CONFIG_PCIE_QCOM_COMMON) += pcie-qcom-common.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rockchip.o
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obj-$(CONFIG_PCIE_SOPHGO_DW) += pcie-sophgo.o
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obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
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obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
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obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
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obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
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obj-$(CONFIG_PCI_MESON) += pci-meson.o
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obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
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obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
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obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
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obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
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obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
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obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
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obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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# They contain MCFG quirks to replace the generic ECAM accessors with
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# device-specific ones that are shared with the DT driver.
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# The ACPI driver is generic and should not require driver-specific
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# config options to be enabled, so we always build these drivers on
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# ARM64 and use internal ifdefs to only build the pieces we need
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# depending on whether ACPI, the DT driver, or both are enabled.
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obj-$(CONFIG_PCIE_AL) += pcie-al.o
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obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
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ifdef CONFIG_ACPI
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ifdef CONFIG_PCI_QUIRKS
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obj-$(CONFIG_ARM64) += pcie-al.o
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obj-$(CONFIG_ARM64) += pcie-hisi.o
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obj-$(CONFIG_ARM64) += pcie-tegra194-acpi.o
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endif
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endif
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