Evan Quan 617a64dc85 drm/amd/powerplay: increase the SMU msg response waiting time ...

This is expected to fix some mode1 reset failures. And this
affects SMU part only as the timeout setting for other parts
is controlled by a different macro.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-07-11 14:37:23 -05:00

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asic_reg

drm/amd/display: Create DWB resource for DCN2

2019-06-22 09:34:11 -05:00

ivsrcid

drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/

2019-06-20 21:35:30 -05:00

amd_acpi.h

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amd_pcie_helpers.h

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amd_pcie.h

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amd_shared.h

drm/amd/powerplay: increase the SMU msg response waiting time

2019-07-11 14:37:23 -05:00

atom-bits.h

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atom-names.h

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atom-types.h

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atombios.h

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atomfirmware.h

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atomfirmwareid.h

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cgs_common.h

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cik_structs.h

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discovery.h

drm/amdgpu/discovery: update definition for struct die_header

2019-06-21 18:58:21 -05:00

displayobject.h

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dm_pp_interface.h

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kgd_kfd_interface.h

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kgd_pp_interface.h

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navi10_enum.h

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navi10_ip_offset.h

drm/amdgpu: add navi10 ip offset header

2019-06-20 15:54:53 -05:00

pptable.h

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soc15_hw_ip.h

drm/amdgpu: add navi10 ip offset header

2019-06-20 15:54:53 -05:00

soc15_ih_clientid.h

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v9_structs.h

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v10_structs.h

drm/amdgpu: add v10 structs header (v2)

2019-06-20 21:16:37 -05:00

vega10_enum.h

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vega10_ip_offset.h

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vega20_ip_offset.h

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vi_structs.h

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