Paul Burton 1e18ac7aea MIPS: c-r4k: Extend way_string array ...

The L2 cache in the I6400 core has 16 ways, so extend the way_string
array to take such caches into account.

[ralf@linux-mips.org: Other already supported CPUs are free to support
more than 8 ways of cache as well.]

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10640/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2015-07-10 11:02:20 +02:00

..

c-octeon.c

…

c-r3k.c

…

c-r4k.c

MIPS: c-r4k: Extend way_string array

2015-07-10 11:02:20 +02:00

c-tx39.c

MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'

2015-06-21 21:52:41 +02:00

cache.c

…

cerr-sb1.c

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cex-gen.S

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cex-oct.S

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cex-sb1.S

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dma-default.c

MIPS: use for_each_sg()

2015-06-21 21:54:34 +02:00

extable.c

…

fault.c

mm/fault, arch: Use pagefault_disable() to check for disabled pagefaults in the handler

2015-05-19 08:39:15 +02:00

gup.c

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highmem.c

sched/preempt, mm/kmap: Explicitly disable/enable preemption in kmap_atomic_*

2015-05-19 08:39:14 +02:00

hugetlbpage.c

mm/hugetlb: reduce arch dependent code about huge_pmd_unshare

2015-06-24 17:49:41 -07:00

init.c

sched/preempt, mm/kmap, MIPS: Disable preemption in kmap_coherent() explicitly

2015-05-19 08:39:15 +02:00

ioremap.c

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Makefile

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mmap.c

mm: expose arch_mmap_rnd when available

2015-04-14 16:49:05 -07:00

page-funcs.S

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page.c

MIPS: Add R16000 detection

2015-04-01 17:22:13 +02:00

pgtable-32.c

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pgtable-64.c

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sc-ip22.c

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sc-mips.c

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sc-r5k.c

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sc-rm7k.c

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tlb-funcs.S

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tlb-r3k.c

MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

2015-06-21 21:52:41 +02:00

tlb-r4k.c

MIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that crept in

2015-06-21 21:53:42 +02:00

tlb-r8k.c

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tlbex-fault.S

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tlbex.c

MIPS: tlbex: Avoid unnecessary _PAGE_PRESENT shifts

2015-06-21 21:53:55 +02:00

uasm-micromips.c

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uasm-mips.c

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uasm.c

…