Clément Léger 940a7bcd4f riscv: fix misaligned access handling of C.SWSP and C.SDSP ...

[ Upstream commit 22e0eb0483 ]

This is a backport of a fix that was done in OpenSBI: ec0559eb315b
("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP").

Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
register, so checking that the rs2 field is non-zero is unnecessary.

Additionally, the previous check was incorrect since it was checking
the immediate field of the instruction instead of the rs2 field.

Fixes: 956d705dd2 ("riscv: Unaligned load/store handling for M_MODE")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231103090223.702340-1-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2023-12-13 18:36:41 +01:00

..

boot

riscv: dts: sifive: fu740: fix size of pcie 32bit memory

2023-01-24 07:22:46 +01:00

configs

RISC-V: defconfigs: Set CONFIG_FB=y, for FB console

2022-07-12 16:34:54 +02:00

errata

…

include

riscv,mmio: Fix readX()-to-delay() ordering

2023-08-16 18:21:58 +02:00

kernel

riscv: fix misaligned access handling of C.SWSP and C.SDSP

2023-12-13 18:36:41 +01:00

lib

riscv: uaccess: Return the number of bytes effectively not copied

2023-08-26 14:23:36 +02:00

mm

riscv: mm: fix truncation warning on RV32

2023-07-23 13:47:45 +02:00

net

riscv, bpf: Sign-extend return values

2023-10-19 23:05:34 +02:00

Kbuild

…

Kconfig

riscv: fix kprobe __user string arg print fault issue

2023-06-14 11:13:09 +02:00

Kconfig.debug

…

Kconfig.erratas

riscv: alternative only works on !XIP_KERNEL

2022-03-16 14:23:42 +01:00

Kconfig.socs

riscv: alternative only works on !XIP_KERNEL

2022-03-16 14:23:42 +01:00

Makefile

riscv: Handle zicsr/zifencei issues between clang and binutils

2023-03-30 12:47:59 +02:00