Austin Zheng c5f78ea8d7 drm/amd/display: Add Clock Table Entry With Max DC Values ...

Why:
Certain display configs resulted in underflow

How:
Add an entry containing all max DC clock timings

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2023-06-23 15:40:50 -04:00

..

dcn32_fpu.c

drm/amd/display: Add Clock Table Entry With Max DC Values

2023-06-23 15:40:50 -04:00

dcn32_fpu.h

drm/amd/display: Add Clock Table Entry With Max DC Values

2023-06-23 15:40:50 -04:00

display_mode_vba_32.c

drm/amd/display: Apply 60us prefetch for DCFCLK <= 300Mhz

2023-06-09 10:44:08 -04:00

display_mode_vba_32.h

drm/amd/display: Apply 60us prefetch for DCFCLK <= 300Mhz

2023-06-09 10:44:08 -04:00

display_mode_vba_util_32.c

drm/amd/display: Add check for PState change in DCN32

2023-04-21 08:50:20 -04:00

display_mode_vba_util_32.h

drm/amd/display: Update to correct min FCLK when construction BB

2023-03-07 14:22:40 -05:00

display_rq_dlg_calc_32.c

drm/amd/display: Fix a test dml32_rq_dlg_get_rq_reg()

2023-06-09 09:20:40 -04:00

display_rq_dlg_calc_32.h

…