Clay King 7d9ec9dc20 drm/amd/display: bypass post csc for additional color spaces in dal ...

[Why]
For RGB BT2020 full and limited color spaces, overlay adjustments were
applied twice (once by MM and once by DAL). This results in incorrect
colours and a noticeable difference between mpo and non-mpo cases.

[How]
Add RGB BT2020 full and limited color spaces to list that bypasses post
csc adjustment.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2026-02-12 15:16:09 -05:00

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dcn10

drm/amd/display: DPP low mem pwr related adjustment -Part I

2025-12-16 13:26:06 -05:00

dcn20

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dcn30

drm/amd/display: bypass post csc for additional color spaces in dal

2026-02-12 15:16:09 -05:00

dcn32

drm/amd/display: Add more DC HW state info to underflow logging

2025-10-28 09:57:44 -04:00

dcn35

drm/amd/display: Add more DC HW state info to underflow logging

2025-10-28 09:57:44 -04:00

dcn201

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dcn401

drm/amd/display: bypass post csc for additional color spaces in dal

2026-02-12 15:16:09 -05:00

Makefile

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