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AngeloGioacchino Del Regno
3c36965df8
Add a driver for the regulators found on the MT6363 PMIC, fully controlled by SPMI interface. This PMIC regulates voltage with an input range of 2.6-5.0V, and features 10 buck converters and 26 LDOs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251027110527.21002-5-angelogioacchino.delregno@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
331 lines
14 KiB
C
331 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 MediaTek Inc.
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* Copyright (c) 2025 Collabora Ltd
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*/
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#include <linux/bits.h>
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#ifndef __LINUX_REGULATOR_MT6363_H
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#define __LINUX_REGULATOR_MT6363_H
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/* Register */
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#define MT6363_TOP_TRAP 0x6
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#define MT6363_TOP_TMA_KEY_L 0x36e
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#define MT6363_RG_BUCK0_EN_ADDR 0x210
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#define MT6363_RG_BUCK_VS2_EN_BIT 0
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#define MT6363_RG_BUCK_VBUCK1_EN_BIT 1
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#define MT6363_RG_BUCK_VBUCK2_EN_BIT 2
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#define MT6363_RG_BUCK_VBUCK3_EN_BIT 3
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#define MT6363_RG_BUCK_VBUCK4_EN_BIT 4
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#define MT6363_RG_BUCK_VBUCK5_EN_BIT 5
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#define MT6363_RG_BUCK_VBUCK6_EN_BIT 6
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#define MT6363_RG_BUCK_VBUCK7_EN_BIT 7
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#define MT6363_RG_BUCK1_EN_ADDR 0x213
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#define MT6363_RG_BUCK_VS1_EN_BIT 0
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#define MT6363_RG_BUCK_VS3_EN_BIT 1
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#define MT6363_RG_LDO_VSRAM_DIGRF_EN_BIT 4
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#define MT6363_RG_LDO_VSRAM_MDFE_EN_BIT 5
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#define MT6363_RG_LDO_VSRAM_MODEM_EN_BIT 6
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#define MT6363_RG_BUCK0_LP_ADDR 0x216
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#define MT6363_RG_BUCK_VS2_LP_BIT 0
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#define MT6363_RG_BUCK_VBUCK1_LP_BIT 1
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#define MT6363_RG_BUCK_VBUCK2_LP_BIT 2
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#define MT6363_RG_BUCK_VBUCK3_LP_BIT 3
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#define MT6363_RG_BUCK_VBUCK4_LP_BIT 4
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#define MT6363_RG_BUCK_VBUCK5_LP_BIT 5
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#define MT6363_RG_BUCK_VBUCK6_LP_BIT 6
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#define MT6363_RG_BUCK_VBUCK7_LP_BIT 7
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#define MT6363_RG_BUCK1_LP_ADDR 0x219
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#define MT6363_RG_BUCK_VS1_LP_BIT 0
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#define MT6363_RG_BUCK_VS3_LP_BIT 1
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#define MT6363_RG_LDO_VSRAM_DIGRF_LP_BIT 4
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#define MT6363_RG_LDO_VSRAM_MDFE_LP_BIT 5
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#define MT6363_RG_LDO_VSRAM_MODEM_LP_BIT 6
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#define MT6363_RG_BUCK_VS2_VOSEL_ADDR 0x21c
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#define MT6363_RG_BUCK_VS2_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK1_VOSEL_ADDR 0x21d
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#define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK2_VOSEL_ADDR 0x21e
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#define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK3_VOSEL_ADDR 0x21f
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#define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR 0x220
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#define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK5_VOSEL_ADDR 0x221
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#define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK6_VOSEL_ADDR 0x222
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#define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VBUCK7_VOSEL_ADDR 0x223
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#define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VS1_VOSEL_ADDR 0x224
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#define MT6363_RG_BUCK_VS1_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_BUCK_VS3_VOSEL_ADDR 0x225
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#define MT6363_RG_BUCK_VS3_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_ADDR 0x228
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#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_ADDR 0x229
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#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_ADDR 0x22a
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#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_BUCK_TOP_KEY_PROT_LO 0x13fa
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#define MT6363_BUCK_VS2_WDTDBG_VOSEL_ADDR 0x13fc
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#define MT6363_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR 0x13fd
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#define MT6363_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR 0x13fe
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#define MT6363_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR 0x13ff
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#define MT6363_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR 0x1400
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#define MT6363_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR 0x1401
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#define MT6363_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR 0x1402
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#define MT6363_BUCK_VBUCK7_WDTDBG_VOSEL_ADDR 0x1403
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#define MT6363_BUCK_VS1_WDTDBG_VOSEL_ADDR 0x1404
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#define MT6363_BUCK_VS3_WDTDBG_VOSEL_ADDR 0x1405
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#define MT6363_RG_BUCK_EFUSE_RSV1 0x1417
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#define MT6363_RG_BUCK_EFUSE_RSV1_MASK GENMASK(7, 4)
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#define MT6363_BUCK_VS2_OP_EN_0 0x145d
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#define MT6363_BUCK_VS2_HW_LP_MODE 0x1468
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#define MT6363_BUCK_VBUCK1_OP_EN_0 0x14dd
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#define MT6363_BUCK_VBUCK1_HW_LP_MODE 0x14e8
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#define MT6363_RG_BUCK_VBUCK1_SSHUB_EN_ADDR 0x14ea
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#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_ADDR 0x14eb
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#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_BUCK_VBUCK2_OP_EN_0 0x155d
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#define MT6363_BUCK_VBUCK2_HW_LP_MODE 0x1568
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#define MT6363_RG_BUCK_VBUCK2_SSHUB_EN_ADDR 0x156a
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#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_ADDR 0x156b
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#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_BUCK_VBUCK3_OP_EN_0 0x15dd
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#define MT6363_BUCK_VBUCK3_HW_LP_MODE 0x15e8
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#define MT6363_BUCK_VBUCK4_OP_EN_0 0x165d
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#define MT6363_BUCK_VBUCK4_HW_LP_MODE 0x1668
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#define MT6363_RG_BUCK_VBUCK4_SSHUB_EN_ADDR 0x166a
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#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR 0x166b
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#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK GENMASK(7, 0)
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#define MT6363_BUCK_VBUCK5_OP_EN_0 0x16dd
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#define MT6363_BUCK_VBUCK5_HW_LP_MODE 0x16e8
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#define MT6363_BUCK_VBUCK6_OP_EN_0 0x175d
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#define MT6363_BUCK_VBUCK6_HW_LP_MODE 0x1768
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#define MT6363_BUCK_VBUCK7_OP_EN_0 0x17dd
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#define MT6363_BUCK_VBUCK7_HW_LP_MODE 0x17e8
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#define MT6363_BUCK_VS1_OP_EN_0 0x185d
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#define MT6363_BUCK_VS1_HW_LP_MODE 0x1868
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#define MT6363_BUCK_VS3_OP_EN_0 0x18dd
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#define MT6363_BUCK_VS3_HW_LP_MODE 0x18e8
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#define MT6363_RG_VS1_FCCM_ADDR 0x1964
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#define MT6363_RG_VS1_FCCM_BIT 0
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#define MT6363_RG_VS3_FCCM_ADDR 0x1973
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#define MT6363_RG_VS3_FCCM_BIT 0
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#define MT6363_RG_BUCK0_FCCM_ADDR 0x1a02
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#define MT6363_RG_VBUCK1_FCCM_BIT 0
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#define MT6363_RG_VBUCK2_FCCM_BIT 1
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#define MT6363_RG_VBUCK3_FCCM_BIT 2
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#define MT6363_RG_VS2_FCCM_BIT 3
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#define MT6363_RG_BUCK0_1_FCCM_ADDR 0x1a82
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#define MT6363_RG_VBUCK4_FCCM_BIT 0
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#define MT6363_RG_VBUCK5_FCCM_BIT 1
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#define MT6363_RG_VBUCK6_FCCM_BIT 2
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#define MT6363_RG_VBUCK7_FCCM_BIT 3
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#define MT6363_RG_VCN13_VOSEL_ADDR 0x1b0f
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#define MT6363_RG_VCN13_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VEMC_VOSEL_ADDR 0x1b10
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#define MT6363_RG_VEMC_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VEMC_VOSEL_1_MASK GENMASK(7, 4)
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#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_ADDR 0x1b14
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#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_ADDR 0x1b15
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#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_ADDR 0x1b16
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#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_RG_LDO_VSRAM_APU_VOSEL_ADDR 0x1b17
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#define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK GENMASK(6, 0)
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#define MT6363_RG_VEMC_VOCAL_ADDR 0x1b1b
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#define MT6363_RG_VEMC_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_LDO_VCN15_ADDR 0x1b57
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#define MT6363_RG_LDO_VCN15_EN_BIT 0
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#define MT6363_RG_LDO_VCN15_LP_BIT 1
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#define MT6363_LDO_VCN15_HW_LP_MODE 0x1b5b
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#define MT6363_LDO_VCN15_OP_EN0 0x1b5c
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#define MT6363_RG_LDO_VRF09_ADDR 0x1b65
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#define MT6363_RG_LDO_VRF09_EN_BIT 0
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#define MT6363_RG_LDO_VRF09_LP_BIT 1
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#define MT6363_LDO_VRF09_HW_LP_MODE 0x1b69
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#define MT6363_LDO_VRF09_OP_EN0 0x1b6a
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#define MT6363_RG_LDO_VRF12_ADDR 0x1b73
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#define MT6363_RG_LDO_VRF12_EN_BIT 0
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#define MT6363_RG_LDO_VRF12_LP_BIT 1
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#define MT6363_LDO_VRF12_HW_LP_MODE 0x1b77
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#define MT6363_LDO_VRF12_OP_EN0 0x1b78
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#define MT6363_RG_LDO_VRF13_ADDR 0x1b81
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#define MT6363_RG_LDO_VRF13_EN_BIT 0
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#define MT6363_RG_LDO_VRF13_LP_BIT 1
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#define MT6363_LDO_VRF13_HW_LP_MODE 0x1b85
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#define MT6363_LDO_VRF13_OP_EN0 0x1b86
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#define MT6363_RG_LDO_VRF18_ADDR 0x1b8f
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#define MT6363_RG_LDO_VRF18_EN_BIT 0
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#define MT6363_RG_LDO_VRF18_LP_BIT 1
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#define MT6363_LDO_VRF18_HW_LP_MODE 0x1b93
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#define MT6363_LDO_VRF18_OP_EN0 0x1b94
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#define MT6363_RG_LDO_VRFIO18_ADDR 0x1b9d
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#define MT6363_RG_LDO_VRFIO18_EN_BIT 0
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#define MT6363_RG_LDO_VRFIO18_LP_BIT 1
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#define MT6363_LDO_VRFIO18_HW_LP_MODE 0x1ba1
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#define MT6363_LDO_VRFIO18_OP_EN0 0x1ba2
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#define MT6363_RG_LDO_VTREF18_ADDR 0x1bd7
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#define MT6363_RG_LDO_VTREF18_EN_BIT 0
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#define MT6363_RG_LDO_VTREF18_LP_BIT 1
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#define MT6363_LDO_VTREF18_HW_LP_MODE 0x1bdb
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#define MT6363_LDO_VTREF18_OP_EN0 0x1bdc
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#define MT6363_RG_LDO_VAUX18_ADDR 0x1be5
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#define MT6363_RG_LDO_VAUX18_EN_BIT 0
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#define MT6363_RG_LDO_VAUX18_LP_BIT 1
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#define MT6363_LDO_VAUX18_HW_LP_MODE 0x1be9
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#define MT6363_LDO_VAUX18_OP_EN0 0x1bea
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#define MT6363_RG_LDO_VEMC_ADDR 0x1bf3
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#define MT6363_RG_LDO_VEMC_EN_BIT 0
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#define MT6363_RG_LDO_VEMC_LP_BIT 1
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#define MT6363_LDO_VEMC_HW_LP_MODE 0x1bf7
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#define MT6363_LDO_VEMC_OP_EN0 0x1bf8
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#define MT6363_RG_LDO_VUFS12_ADDR 0x1c01
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#define MT6363_RG_LDO_VUFS12_EN_BIT 0
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#define MT6363_RG_LDO_VUFS12_LP_BIT 1
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#define MT6363_LDO_VUFS12_HW_LP_MODE 0x1c05
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#define MT6363_LDO_VUFS12_OP_EN0 0x1c06
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#define MT6363_RG_LDO_VUFS18_ADDR 0x1c0f
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#define MT6363_RG_LDO_VUFS18_EN_BIT 0
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#define MT6363_RG_LDO_VUFS18_LP_BIT 1
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#define MT6363_LDO_VUFS18_HW_LP_MODE 0x1c13
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#define MT6363_LDO_VUFS18_OP_EN0 0x1c14
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#define MT6363_RG_LDO_VIO18_ADDR 0x1c1d
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#define MT6363_RG_LDO_VIO18_EN_BIT 0
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#define MT6363_RG_LDO_VIO18_LP_BIT 1
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#define MT6363_LDO_VIO18_HW_LP_MODE 0x1c21
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#define MT6363_LDO_VIO18_OP_EN0 0x1c22
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#define MT6363_RG_LDO_VIO075_ADDR 0x1c57
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#define MT6363_RG_LDO_VIO075_EN_BIT 0
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#define MT6363_RG_LDO_VIO075_LP_BIT 1
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#define MT6363_LDO_VIO075_HW_LP_MODE 0x1c5b
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#define MT6363_LDO_VIO075_OP_EN0 0x1c5c
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#define MT6363_RG_LDO_VA12_1_ADDR 0x1c65
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#define MT6363_RG_LDO_VA12_1_EN_BIT 0
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#define MT6363_RG_LDO_VA12_1_LP_BIT 1
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#define MT6363_LDO_VA12_1_HW_LP_MODE 0x1c69
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#define MT6363_LDO_VA12_1_OP_EN0 0x1c6a
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#define MT6363_RG_LDO_VA12_2_ADDR 0x1c73
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#define MT6363_RG_LDO_VA12_2_EN_BIT 0
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#define MT6363_RG_LDO_VA12_2_LP_BIT 1
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#define MT6363_LDO_VA12_2_HW_LP_MODE 0x1c77
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#define MT6363_LDO_VA12_2_OP_EN0 0x1c78
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#define MT6363_RG_LDO_VA15_ADDR 0x1c81
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#define MT6363_RG_LDO_VA15_EN_BIT 0
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#define MT6363_RG_LDO_VA15_LP_BIT 1
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#define MT6363_LDO_VA15_HW_LP_MODE 0x1c85
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#define MT6363_LDO_VA15_OP_EN0 0x1c86
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#define MT6363_RG_LDO_VM18_ADDR 0x1c8f
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#define MT6363_RG_LDO_VM18_EN_BIT 0
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#define MT6363_RG_LDO_VM18_LP_BIT 1
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#define MT6363_LDO_VM18_HW_LP_MODE 0x1c93
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#define MT6363_LDO_VM18_OP_EN0 0x1c94
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#define MT6363_RG_LDO_VCN13_ADDR 0x1cd7
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#define MT6363_RG_LDO_VCN13_EN_BIT 0
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#define MT6363_RG_LDO_VCN13_LP_BIT 1
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#define MT6363_LDO_VCN13_HW_LP_MODE 0x1cdb
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#define MT6363_LDO_VCN13_OP_EN0 0x1ce4
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#define MT6363_LDO_VSRAM_DIGRF_HW_LP_MODE 0x1cf1
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#define MT6363_LDO_VSRAM_DIGRF_OP_EN0 0x1cfa
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#define MT6363_LDO_VSRAM_MDFE_HW_LP_MODE 0x1d5b
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#define MT6363_LDO_VSRAM_MDFE_OP_EN0 0x1d64
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#define MT6363_LDO_VSRAM_MODEM_HW_LP_MODE 0x1d76
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#define MT6363_LDO_VSRAM_MODEM_OP_EN0 0x1d7f
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#define MT6363_RG_LDO_VSRAM_CPUB_ADDR 0x1dd7
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#define MT6363_RG_LDO_VSRAM_CPUB_EN_BIT 0
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#define MT6363_RG_LDO_VSRAM_CPUB_LP_BIT 1
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#define MT6363_LDO_VSRAM_CPUB_HW_LP_MODE 0x1ddb
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#define MT6363_LDO_VSRAM_CPUB_OP_EN0 0x1de4
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#define MT6363_RG_LDO_VSRAM_CPUM_ADDR 0x1ded
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#define MT6363_RG_LDO_VSRAM_CPUM_EN_BIT 0
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#define MT6363_RG_LDO_VSRAM_CPUM_LP_BIT 1
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#define MT6363_LDO_VSRAM_CPUM_HW_LP_MODE 0x1df1
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#define MT6363_LDO_VSRAM_CPUM_OP_EN0 0x1dfa
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#define MT6363_RG_LDO_VSRAM_CPUL_ADDR 0x1e57
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#define MT6363_RG_LDO_VSRAM_CPUL_EN_BIT 0
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#define MT6363_RG_LDO_VSRAM_CPUL_LP_BIT 1
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#define MT6363_LDO_VSRAM_CPUL_HW_LP_MODE 0x1e5b
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#define MT6363_LDO_VSRAM_CPUL_OP_EN0 0x1e64
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#define MT6363_RG_LDO_VSRAM_APU_ADDR 0x1e6d
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#define MT6363_RG_LDO_VSRAM_APU_EN_BIT 0
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#define MT6363_RG_LDO_VSRAM_APU_LP_BIT 1
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#define MT6363_LDO_VSRAM_APU_HW_LP_MODE 0x1e71
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#define MT6363_LDO_VSRAM_APU_OP_EN0 0x1e7a
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#define MT6363_RG_VTREF18_VOCAL_ADDR 0x1ed8
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#define MT6363_RG_VTREF18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VTREF18_VOSEL_ADDR 0x1ed9
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#define MT6363_RG_VTREF18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VAUX18_VOCAL_ADDR 0x1edc
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#define MT6363_RG_VAUX18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VAUX18_VOSEL_ADDR 0x1edd
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#define MT6363_RG_VAUX18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VCN15_VOCAL_ADDR 0x1ee3
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#define MT6363_RG_VCN15_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VCN15_VOSEL_ADDR 0x1ee4
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#define MT6363_RG_VCN15_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VUFS18_VOCAL_ADDR 0x1ee7
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#define MT6363_RG_VUFS18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VUFS18_VOSEL_ADDR 0x1ee8
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#define MT6363_RG_VUFS18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VIO18_VOCAL_ADDR 0x1eeb
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#define MT6363_RG_VIO18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VIO18_VOSEL_ADDR 0x1eec
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#define MT6363_RG_VIO18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VM18_VOCAL_ADDR 0x1eef
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#define MT6363_RG_VM18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VM18_VOSEL_ADDR 0x1ef0
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#define MT6363_RG_VM18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VA15_VOCAL_ADDR 0x1ef3
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#define MT6363_RG_VA15_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VA15_VOSEL_ADDR 0x1ef4
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#define MT6363_RG_VA15_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF18_VOCAL_ADDR 0x1ef7
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#define MT6363_RG_VRF18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF18_VOSEL_ADDR 0x1ef8
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#define MT6363_RG_VRF18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRFIO18_VOCAL_ADDR 0x1efb
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#define MT6363_RG_VRFIO18_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRFIO18_VOSEL_ADDR 0x1efc
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#define MT6363_RG_VRFIO18_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VIO075_VOCFG_ADDR 0x1f01
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#define MT6363_RG_VIO075_VOCAL_ADDR MT6363_RG_VIO075_VOCFG_ADDR
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#define MT6363_RG_VIO075_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VIO075_VOSEL_ADDR MT6363_RG_VIO075_VOCFG_ADDR
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#define MT6363_RG_VIO075_VOSEL_MASK GENMASK(6, 4)
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#define MT6363_RG_VCN13_VOCAL_ADDR 0x1f58
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#define MT6363_RG_VCN13_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VUFS12_VOCAL_ADDR 0x1f61
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#define MT6363_RG_VUFS12_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VUFS12_VOSEL_ADDR 0x1f62
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#define MT6363_RG_VUFS12_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VA12_1_VOCAL_ADDR 0x1f65
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#define MT6363_RG_VA12_1_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VA12_1_VOSEL_ADDR 0x1f66
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#define MT6363_RG_VA12_1_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VA12_2_VOCAL_ADDR 0x1f69
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#define MT6363_RG_VA12_2_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VA12_2_VOSEL_ADDR 0x1f6a
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#define MT6363_RG_VA12_2_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF12_VOCAL_ADDR 0x1f6d
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#define MT6363_RG_VRF12_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF12_VOSEL_ADDR 0x1f6e
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#define MT6363_RG_VRF12_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF13_VOCAL_ADDR 0x1f71
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#define MT6363_RG_VRF13_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF13_VOSEL_ADDR 0x1f72
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#define MT6363_RG_VRF13_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF09_VOCAL_ADDR 0x1f78
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#define MT6363_RG_VRF09_VOCAL_MASK GENMASK(3, 0)
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#define MT6363_RG_VRF09_VOSEL_ADDR 0x1f79
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#define MT6363_RG_VRF09_VOSEL_MASK GENMASK(3, 0)
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#define MT6363_ISINK_EN_CTRL0 0x21db
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#define MT6363_ISINK_CTRL0_MASK GENMASK(7, 0)
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#define MT6363_ISINK_EN_CTRL1 0x21dc
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#define MT6363_ISINK_CTRL1_MASK GENMASK(7, 4)
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#endif /* __LINUX_REGULATOR_MT6363_H */
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