Alex Deucher 7be89985c4 drm/amdgpu: add Green_Sardine APU flag ...

Will be used for Green_Sardine which is a new APU.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-11-04 08:30:48 -05:00

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asic_reg

drm/amdgpu: update athub interrupt harvesting handle

2020-09-22 17:37:38 -04:00

ivsrcid

drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)

2020-06-03 13:52:03 -04:00

amd_acpi.h

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amd_pcie_helpers.h

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amd_pcie.h

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amd_shared.h

drm/amdgpu: add Green_Sardine APU flag

2020-11-04 08:30:48 -05:00

arct_ip_offset.h

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atom-bits.h

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atom-names.h

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atom-types.h

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atombios.h

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atomfirmware.h

drm/amd/display: Read VBIOS Golden Settings Tbl

2020-08-06 16:47:13 -04:00

atomfirmwareid.h

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cgs_common.h

drm/amdgpu: retire indirect mmio reg support from cgs

2020-04-09 10:43:18 -04:00

cik_structs.h

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discovery.h

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displayobject.h

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dm_pp_interface.h

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kgd_kfd_interface.h

Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm

2020-10-15 10:46:16 -07:00

kgd_pp_interface.h

drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU.

2020-09-29 16:12:16 -04:00

navi10_enum.h

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navi10_ip_offset.h

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navi12_ip_offset.h

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navi14_ip_offset.h

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pptable.h

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renoir_ip_offset.h

drm/amd/display: Add DCN_BASE regs

2019-10-17 16:27:27 -04:00

sienna_cichlid_ip_offset.h

drm/amdgpu: initialize IP offset for sienna_cichlid (v2)

2020-06-03 13:52:00 -04:00

soc15_hw_ip.h

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soc15_ih_clientid.h

drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid

2020-06-03 13:52:04 -04:00

v9_structs.h

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v10_structs.h

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vega10_enum.h

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vega10_ip_offset.h

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vega20_ip_offset.h

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vi_structs.h

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