Pierre-Louis Bossart 2fb9478495 soundwire: registers: add definitions for clearable interrupt fields ...

DP0 has reserved fields and the read-only SDCA_CASCADE bit. We should
not try to write values in these fields, so add a formal definition
for clearable interrupts to be used in DP0 interrupt handling.

DPN also has reserved fields so add definitions for clearable
interrupts as well.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20201124013318.8963-4-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

2020-11-25 10:32:25 +05:30

..

sdw_intel.h

soundwire: intel: revisit SHIM programming sequences.

2020-07-21 16:05:40 +05:30

sdw_registers.h

soundwire: registers: add definitions for clearable interrupt fields

2020-11-25 10:32:25 +05:30

sdw_type.h

soundwire: bus_type: introduce sdw_slave_type and sdw_master_type

2020-05-19 12:44:34 +05:30

sdw.h

soundwire: SDCA: detect sdca_cascade interrupt

2020-11-24 14:09:31 +05:30