Alex Deucher 8284a9e917 drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.h ...

This should be MIT.  The driver in general is MIT and
the license text at the top of the file is MIT so fix
it.

Fixes: d1bb646510 ("drm/amdgpu: add irq source ids for VCN5_0/JPEG5_0")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 68c20d7b17)

2025-10-28 11:02:49 -04:00

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asic_reg

drm/amdgpu: Add additional DCE6 SCL registers

2025-10-07 14:09:06 -04:00

ivsrcid

drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.h

2025-10-28 11:02:49 -04:00

aldebaran_ip_offset.h

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amd_acpi.h

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amd_cper.h

drm/amdgpu: fix SPDX header on amd_cper.h

2025-10-28 11:02:42 -04:00

amd_pcie_helpers.h

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amd_pcie.h

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amd_shared.h

drm/amd: Duplicate DC_FEATURE_MASK and DC_DEBUG_MASK enum values into kdoc

2025-09-15 16:56:04 -04:00

amdgpu_reg_state.h

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arct_ip_offset.h

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atom-bits.h

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atom-names.h

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atom-types.h

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atombios.h

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atomfirmware.h

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atomfirmwareid.h

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beige_goby_ip_offset.h

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cgs_common.h

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cik_structs.h

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cyan_skillfish_ip_offset.h

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dimgrey_cavefish_ip_offset.h

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discovery.h

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displayobject.h

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dm_pp_interface.h

drm/amd/display: Add pixel_clock to amd_pp_display_configuration

2025-09-15 16:52:41 -04:00

kgd_kfd_interface.h

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kgd_pp_interface.h

drm/amd/pm: Add sysfs node for node power

2025-09-18 09:43:02 -04:00

mes_v11_api_def.h

drm/amdgpu: Enable MES lr_compute_wa by default

2025-09-23 10:22:38 -04:00

mes_v12_api_def.h

drm/amdgpu: Enable MES lr_compute_wa by default

2025-09-23 10:22:38 -04:00

navi10_enum.h

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navi10_ip_offset.h

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navi12_ip_offset.h

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navi14_ip_offset.h

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pptable.h

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renoir_ip_offset.h

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sienna_cichlid_ip_offset.h

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soc15_hw_ip.h

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soc15_ih_clientid.h

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soc21_enum.h

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soc24_enum.h

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umsch_mm_4_0_api_def.h

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v9_structs.h

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v10_structs.h

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v11_structs.h

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v12_structs.h

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vangogh_ip_offset.h

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vega10_enum.h

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vega10_ip_offset.h

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vega20_ip_offset.h

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vi_structs.h

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yellow_carp_offset.h

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