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The LAN8842 is a low-power, single port triple-speed (10BASE-T/ 100BASE-TX/ 1000BASE-T) ethernet physical layer transceiver (PHY) that supports transmission and reception of data on standard CAT-5, as well as CAT-5e and CAT-6, Unshielded Twisted Pair (UTP) cables. The LAN8842 supports industry-standard SGMII (Serial Gigabit Media Independent Interface) providing chip-to-chip connection to a Gigabit Ethernet MAC using a single serialized link (differential pair) in each direction. There are 2 variants of the lan8842. The one that supports timestamping (lan8842) and one that doesn't have timestamping (lan8832). Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250818075121.1298170-5-horatiu.vultur@microchip.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
74 lines
2.1 KiB
C
74 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/linux/micrel_phy.h
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*
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* Micrel PHY IDs
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*/
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#ifndef _MICREL_PHY_H
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#define _MICREL_PHY_H
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#define MICREL_OUI 0x0885
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#define MICREL_PHY_ID_MASK 0x00fffff0
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#define PHY_ID_KSZ8873MLL 0x000e7237
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#define PHY_ID_KSZ9021 0x00221610
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#define PHY_ID_KSZ9021RLRN 0x00221611
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#define PHY_ID_KS8737 0x00221720
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#define PHY_ID_KSZ8021 0x00221555
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#define PHY_ID_KSZ8031 0x00221556
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#define PHY_ID_KSZ8041 0x00221510
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/* undocumented */
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#define PHY_ID_KSZ8041RNLI 0x00221537
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#define PHY_ID_KSZ8051 0x00221550
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/* same id: ks8001 Rev. A/B, and ks8721 Rev 3. */
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#define PHY_ID_KSZ8001 0x0022161A
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/* same id: KS8081, KS8091 */
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#define PHY_ID_KSZ8081 0x00221560
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#define PHY_ID_KSZ8061 0x00221570
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#define PHY_ID_KSZ9031 0x00221620
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#define PHY_ID_KSZ9131 0x00221640
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#define PHY_ID_LAN8814 0x00221660
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#define PHY_ID_LAN8804 0x00221670
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#define PHY_ID_LAN8841 0x00221650
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#define PHY_ID_LAN8842 0x002216C0
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#define PHY_ID_KSZ886X 0x00221430
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#define PHY_ID_KSZ8863 0x00221435
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#define PHY_ID_KSZ87XX 0x00221550
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#define PHY_ID_KSZ9477 0x00221631
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/* struct phy_device dev_flags definitions */
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#define MICREL_PHY_50MHZ_CLK BIT(0)
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#define MICREL_PHY_FXEN BIT(1)
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#define MICREL_KSZ8_P1_ERRATA BIT(2)
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#define MICREL_KSZ9021_EXTREG_CTRL 0xB
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#define MICREL_KSZ9021_EXTREG_DATA_WRITE 0xC
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#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
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#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW 0x105
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/* Device specific MII_BMCR (Reg 0) bits */
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/* 1 = HP Auto MDI/MDI-X mode, 0 = Microchip Auto MDI/MDI-X mode */
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#define KSZ886X_BMCR_HP_MDIX BIT(5)
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/* 1 = Force MDI (transmit on RXP/RXM pins), 0 = Normal operation
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* (transmit on TXP/TXM pins)
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*/
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#define KSZ886X_BMCR_FORCE_MDI BIT(4)
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/* 1 = Disable auto MDI-X */
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#define KSZ886X_BMCR_DISABLE_AUTO_MDIX BIT(3)
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#define KSZ886X_BMCR_DISABLE_FAR_END_FAULT BIT(2)
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#define KSZ886X_BMCR_DISABLE_TRANSMIT BIT(1)
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#define KSZ886X_BMCR_DISABLE_LED BIT(0)
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/* PHY Special Control/Status Register (Reg 31) */
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#define KSZ886X_CTRL_MDIX_STAT BIT(4)
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#define KSZ886X_CTRL_FORCE_LINK BIT(3)
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#define KSZ886X_CTRL_PWRSAVE BIT(2)
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#define KSZ886X_CTRL_REMOTE_LOOPBACK BIT(1)
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#endif /* _MICREL_PHY_H */
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