Christophe Leroy e7dd8ba6fc powerpc/40x: Map 32Mbytes of memory at startup ...

[ Upstream commit 06e7cbc29e ]

As reported by Carlo, 16Mbytes is not enough with modern kernels
that tend to be a bit big, so map another 16M page at boot.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/89b5f974a7fa5011206682cd092e2c905530ff46.1632755552.git.christophe.leroy@csgroup.eu
Signed-off-by: Sasha Levin <sashal@kernel.org>

2022-01-27 11:05:01 +01:00

..

alpha

…

arc

signal: Replace force_sigsegv(SIGSEGV) with force_fatal_sig(SIGSEGV)

2021-11-25 09:49:06 +01:00

arm

ARM: dts: qcom: sdx55: fix IPA interconnect definitions

2022-01-27 11:04:39 +01:00

arm64

arm64: tegra: Adjust length of CCPLEX cluster MMIO region

2022-01-27 11:04:43 +01:00

csky

perf: Protect perf_guest_cbs with RCU

2022-01-20 09:13:14 +01:00

h8300

…

hexagon

…

ia64

…

m68k

signal: Replace force_fatal_sig with force_exit_sig when in doubt

2021-11-25 09:49:07 +01:00

microblaze

…

mips

MIPS: Loongson64: Use three arguments for slti

2022-01-27 11:05:01 +01:00

nds32

perf: Protect perf_guest_cbs with RCU

2022-01-20 09:13:14 +01:00

nios2

…

openrisc

openrisc: Add clone3 ABI wrapper

2022-01-27 11:04:10 +01:00

parisc

parisc: Avoid calling faulthandler_disabled() twice

2022-01-27 11:04:55 +01:00

powerpc

powerpc/40x: Map 32Mbytes of memory at startup

2022-01-27 11:05:01 +01:00

riscv

riscv: mm: fix wrong phys_ram_base value for RV64

2022-01-27 11:02:50 +01:00

s390

KVM: s390: Clarify SIGP orders versus STOP/RESTART

2022-01-20 09:13:14 +01:00

sh

…

sparc

signal: Replace force_fatal_sig with force_exit_sig when in doubt

2021-11-25 09:49:07 +01:00

um

um: registers: Rename function names to avoid conflicts and build problems

2022-01-27 11:04:48 +01:00

x86

x86/kbuild: Enable CONFIG_KALLSYMS_ALL=y in the defconfigs

2022-01-27 11:04:56 +01:00

xtensa

…

.gitignore

…

Kconfig

…