Dinh Nguyen d17929eb10 clk: socfpga: agilex: add the bypass register for s2f_usr0 clock ...

Add the bypass register for the s2f_user0_clk.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2021-07-26 17:56:21 -07:00

..

clk-agilex.c

clk: socfpga: agilex: add the bypass register for s2f_usr0 clock

2021-07-26 17:56:21 -07:00

clk-gate-a10.c

clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return

2021-04-07 16:29:31 -07:00

clk-gate-s10.c

clk: agilex/stratix10: add support for the 2nd bypass

2021-06-27 16:39:59 -07:00

clk-gate.c

Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next

2021-04-27 16:34:28 -07:00

clk-periph-a10.c

clk: socfpga: arria10: convert to use clk_hw

2021-03-30 19:26:26 -07:00

clk-periph-s10.c

clk: agilex/stratix10/n5x: fix how the bypass_reg is handled

2021-06-27 16:39:59 -07:00

clk-periph.c

clk: socfpga: use clk_hw_register for a5/c5

2021-03-30 19:26:26 -07:00

clk-pll-a10.c

clk: socfpga: arria10: convert to use clk_hw

2021-03-30 19:26:26 -07:00

clk-pll-s10.c

clk: socfpga: remove redundant initialization of variable div

2021-04-07 16:30:23 -07:00

clk-pll.c

clk: socfpga: clk-pll: Remove unused variable 'rc'

2021-06-27 17:33:21 -07:00

clk-s10.c

clk: agilex/stratix10: fix bypass representation

2021-06-27 16:39:59 -07:00

clk.c

…

clk.h

…

Kconfig

clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)

2021-03-23 11:03:36 -05:00

Makefile

clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)

2021-03-23 11:03:36 -05:00

stratix10-clk.h

clk: agilex/stratix10: add support for the 2nd bypass

2021-06-27 16:39:59 -07:00