Swapnil Jakhade 8b5d69613b phy: cadence: Sierra: Fix to get correct parent for mux clocks ...

[ Upstream commit da08aab940 ]

Fix get_parent() callback to return the correct index of the parent for
PLL_CMNLC1 clock. Add a separate table of register values corresponding
to the parent index for PLL_CMNLC1. Update set_parent() callback
accordingly.

Fixes: 28081b7285 ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)")
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2022-01-27 11:04:16 +01:00

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cdns-dphy.c

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Kconfig

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Makefile

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phy-cadence-salvo.c

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phy-cadence-sierra.c

phy: cadence: Sierra: Fix to get correct parent for mux clocks

2022-01-27 11:04:16 +01:00

phy-cadence-torrent.c

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