Paul HsiehandGreg Kroah-Hartman f17f0100f7 drm/amd/display: update dpp/disp clock from smu clock table ...

[ Upstream commit 2e72fdba8a ]

[Why]
The reason some high-resolution monitors fail to display properly
is that this platform does not support sufficiently high DPP and
DISP clock frequencies

[How]
Update DISP and DPP clocks from the smu clock table then DML can
filter these mode if not support.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2025-11-24 10:29:24 +01:00

..

amdgpu_dm

drm/amd/display: Avoid a NULL pointer dereference

2025-08-28 16:28:43 +02:00

dc

drm/amd/display: update dpp/disp clock from smu clock table

2025-11-24 10:29:24 +01:00

dmub

…

include

drm/amd/display: add more cyan skillfish devices

2025-11-24 10:29:24 +01:00

modules

minmax: make generic MIN() and MAX() macros available everywhere

2025-10-02 13:42:55 +02:00

Kconfig

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Makefile

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TODO

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