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6dc5fe212e
Internal PCIe errors are not enabled by default during initialization because their behavior is too device-specific and there is no standard way to reason about them. However, for CXL an internal error is the standard mechanism for conveying CXL protocol errors. Export pci_aer_unmask_internal_errors() for CXL, but make it clear that they are only meant for CXL and the status quo for leaving them masked for PCIe in general remains. Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260114182055.46029-10-terry.bowman@amd.com Co-developed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
76 lines
1.9 KiB
C
76 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2006 Intel Corp.
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* Tom Long Nguyen (tom.l.nguyen@intel.com)
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* Zhang Yanmin (yanmin.zhang@intel.com)
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*/
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#ifndef _AER_H_
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#define _AER_H_
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#include <linux/errno.h>
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#include <linux/types.h>
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#define AER_NONFATAL 0
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#define AER_FATAL 1
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#define AER_CORRECTABLE 2
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#define DPC_FATAL 3
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/*
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* AER and DPC capabilities TLP Logging register sizes (PCIe r6.2, sec 7.8.4
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* & 7.9.14).
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*/
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#define PCIE_STD_NUM_TLP_HEADERLOG 4
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#define PCIE_STD_MAX_TLP_PREFIXLOG 4
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#define PCIE_STD_MAX_TLP_HEADERLOG (PCIE_STD_NUM_TLP_HEADERLOG + 10)
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struct pci_dev;
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struct pcie_tlp_log {
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union {
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u32 dw[PCIE_STD_MAX_TLP_HEADERLOG];
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struct {
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u32 _do_not_use[PCIE_STD_NUM_TLP_HEADERLOG];
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u32 prefix[PCIE_STD_MAX_TLP_PREFIXLOG];
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};
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};
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u8 header_len; /* Length of the Logged TLP Header in DWORDs */
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bool flit; /* TLP was logged when in Flit mode */
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};
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struct aer_capability_regs {
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u32 header;
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u32 uncor_status;
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u32 uncor_mask;
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u32 uncor_severity;
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u32 cor_status;
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u32 cor_mask;
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u32 cap_control;
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struct pcie_tlp_log header_log;
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u32 root_command;
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u32 root_status;
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u16 cor_err_source;
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u16 uncor_err_source;
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};
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#if defined(CONFIG_PCIEAER)
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int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
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int pcie_aer_is_native(struct pci_dev *dev);
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void pci_aer_unmask_internal_errors(struct pci_dev *dev);
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#else
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static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
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{
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return -EINVAL;
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}
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static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
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static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }
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#endif
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void pci_print_aer(struct pci_dev *dev, int aer_severity,
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struct aer_capability_regs *aer);
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int cper_severity_to_aer(int cper_severity);
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void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
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int severity, struct aer_capability_regs *aer_regs);
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#endif //_AER_H_
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