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McASP has dedicated clock & frame sync registers for both transmit and receive. Currently McASP driver only supports synchronous behavior and couples both TX & RX settings. Add logic that enables asynchronous mode via ti,async-mode property. In async mode, playback & record can be done simultaneously with different audio configurations (tdm slots, tdm width, audio bit depth). Note the ability to have different tx/rx DSP formats (i2s, dsp_a, etc.), while possible in hardware, remains to be a gap as it require changes to the corresponding machine driver interface. Existing IIS (sync mode) and DIT mode logic remains mostly unchanged. Exceptions are IIS mode logic that previously assumed sync mode, which has now been made aware of the distinction. And shared logic across all modes also now checks for McASP tx/rx-specific driver attributes. Those attributes have been populated according to the original extent, ensuring no divergence in functionality. Constraints no longer applicable for async mode are skipped. Clock selection options have also been added to include rx/tx-only clk_ids, exposing independent configuration via the machine driver as well. Note that asynchronous mode is not applicable for McASP in DIT mode, which is a transmitter-only mode to interface w/ self-clocking formats. Signed-off-by: Sen Wang <sen@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Tested-by: Paresh Bhagat <p-bhagat@ti.com> Link: https://patch.msgid.link/20260203003703.2334443-5-sen@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TI DaVinci Audio Serial Port support
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __DAVINCI_ASP_H
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#define __DAVINCI_ASP_H
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#include <linux/genalloc.h>
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struct davinci_mcasp_pdata {
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u32 tx_dma_offset;
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u32 rx_dma_offset;
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int asp_chan_q; /* event queue number for ASP channel */
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int ram_chan_q; /* event queue number for RAM channel */
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/*
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* Allowing this is more efficient and eliminates left and right swaps
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* caused by underruns, but will swap the left and right channels
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* when compared to previous behavior.
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*/
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unsigned enable_channel_combine:1;
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unsigned sram_size_playback;
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unsigned sram_size_capture;
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struct gen_pool *sram_pool;
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/*
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* This flag works when both clock and FS are outputs for the cpu
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* and makes clock more accurate (FS is not symmetrical and the
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* clock is very fast.
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* The clock becoming faster is named
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* i2s continuous serial clock (I2S_SCK) and it is an externally
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* visible bit clock.
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*
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* first line : WordSelect
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* second line : ContinuousSerialClock
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* third line: SerialData
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*
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* SYMMETRICAL APPROACH:
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* _______________________ LEFT
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* _| RIGHT |______________________|
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* _ _ _ _ _ _ _ _
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* _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
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* _ _ _ _ _ _ _ _
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* _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
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* \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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*
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* ACCURATE CLOCK APPROACH:
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* ______________ LEFT
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* _| RIGHT |_______________________________|
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* _ _ _ _ _ _ _ _ _
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* _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
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* _ _ _ _ dummy cycles
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* _/ \_ ... _/ \_/ \_ ... _/ \__________________
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* \_/ \_/ \_/ \_/
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*
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*/
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bool i2s_accurate_sck;
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/* McASP specific fields */
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int tdm_slots_tx;
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int tdm_slots_rx;
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u8 op_mode;
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u8 dismod;
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u8 num_serializer;
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u8 *serial_dir;
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u8 version;
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u8 txnumevt;
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u8 rxnumevt;
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int tx_dma_channel;
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int rx_dma_channel;
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};
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/* TODO: Fix arch/arm/mach-davinci/ users and remove this define */
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#define snd_platform_data davinci_mcasp_pdata
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enum {
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MCASP_VERSION_1 = 0, /* DM646x */
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MCASP_VERSION_2, /* DA8xx/OMAPL1x */
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MCASP_VERSION_3, /* TI81xx/AM33xx */
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MCASP_VERSION_4, /* DRA7xxx */
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MCASP_VERSION_OMAP, /* OMAP4/5 */
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};
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#define INACTIVE_MODE 0
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#define TX_MODE 1
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#define RX_MODE 2
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#define DAVINCI_MCASP_IIS_MODE 0
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#define DAVINCI_MCASP_DIT_MODE 1
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#endif
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