From 6bd9bceedb6fe9287c09da8db4e1bb67ed5700a6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Samuel=20Mar=C3=ADn=20Soto?= <samarin@estudiantec.cr>
Date: Sat, 2 May 2026 20:20:42 -0600
Subject: [PATCH] linux-headers: build on riscv64

add riscv64 to arches and generated riscv.lua, just like with aarch64
and x86_64.
---
 pkg/linux-headers/gen.lua   |  1 +
 pkg/linux-headers/riscv.lua | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 pkg/linux-headers/riscv.lua

diff --git a/pkg/linux-headers/gen.lua b/pkg/linux-headers/gen.lua
index 346e89fd..1ba46f03 100644
--- a/pkg/linux-headers/gen.lua
+++ b/pkg/linux-headers/gen.lua
@@ -1,6 +1,7 @@
 local arch = ({
 	aarch64='arm64',
 	x86_64='x86',
+	riscv64='riscv',
 })[config.target.platform:match('[^-]*')]
 sub('tools.ninja', function()
 	toolchain(config.host)
diff --git a/pkg/linux-headers/riscv.lua b/pkg/linux-headers/riscv.lua
new file mode 100644
index 00000000..f93b6f15
--- /dev/null
+++ b/pkg/linux-headers/riscv.lua
@@ -0,0 +1,34 @@
+return {
+	-- <cd src/arch/riscv/include/uapi && find * -name '*.h' -exec printf "\t'%s',\n" {} + | LC_COLLATE=C sort
+	'asm/auxvec.h',
+	'asm/bitsperlong.h',
+	'asm/bpf_perf_event.h',
+	'asm/byteorder.h',
+	'asm/elf.h',
+	'asm/hwcap.h',
+	'asm/hwprobe.h',
+	'asm/kvm.h',
+	'asm/perf_regs.h',
+	'asm/ptrace.h',
+	'asm/setup.h',
+	'asm/sigcontext.h',
+	'asm/ucontext.h',
+	'asm/unistd.h',
+	'asm/vendor/mips.h',
+	'asm/vendor/sifive.h',
+	'asm/vendor/thead.h',
+	unistd = {
+		-- arch/riscv/kernel/Makefile.syscalls
+		{
+			dst='unistd_32.h',
+			src='scripts/syscall.tbl',
+			abi='common|32|riscv|memfd_secret',
+		},
+		{
+			dst='unistd_64.h',
+			src='scripts/syscall.tbl',
+			abi='common|64|riscv|rlimit|memfd_secret',
+		},
+	},
+	generic={},
+}