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SIL: Treat -1 as signed when using it to construct an "all bits set" llvm::APInt

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This should enable us to revert
73c70ee338.
This commit is contained in:
Anthony Latsis
2025-08-27 15:18:14 +01:00
parent 26540ca439
commit 2bfe2bd587
6 changed files with 21 additions and 14 deletions
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6
lib/SILOptimizer/Transforms/SimplifyCFG.cpp
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@@ -304,7 +304,8 @@ static SILValue createValueForEdge(SILInstruction *UserInst,
if (auto *CBI = dyn_cast<CondBranchInst>(DominatingTerminator))
return Builder.createIntegerLiteral(
CBI->getLoc(), CBI->getCondition()->getType(), EdgeIdx == 0 ? -1 : 0);
CBI->getLoc(), CBI->getCondition()->getType(), EdgeIdx == 0 ? -1 : 0,
/*treatAsSigned=*/true);
auto *SEI = cast<SwitchEnumInst>(DominatingTerminator);
auto *DstBlock = SEI->getSuccessors()[EdgeIdx].getBB();
@@ -1480,7 +1481,8 @@ static SILValue invertExpectAndApplyTo(SILBuilder &Builder,
if (!IL)
return V;
SILValue NegatedExpectedValue = Builder.createIntegerLiteral(
IL->getLoc(), Args[1]->getType(), IL->getValue() == 0 ? -1 : 0);
IL->getLoc(), Args[1]->getType(), IL->getValue() == 0 ? -1 : 0,
/*treatAsSigned=*/true);
return Builder.createBuiltin(BI->getLoc(), BI->getName(), BI->getType(), {},
{V, NegatedExpectedValue});
}