[sil] Add the ability for the frontend to dump LoweredSIL before IRGen.

This is something that I have wanted to add for a while and have never had the
need to. I need it now to fix a bug in the bots where I am forced to use IRGen
output to test ThunkLowering which causes platform level differences to show up
in the FileCheck output. With this, I can just emit the actual lowered SIL
output and just test it at that level. There are other cases like this where we
are unable to test lowered SIL so we use IRGen creating this brittleness.
Hopefully this stops this problem from showing up in the future.

rdar://138845396

include/swift/Basic/FileTypes.def

@@ -56,6 +56,7 @@ TYPE("swiftmodulesummary",  SwiftModuleSummaryFile,    "swiftmodulesummary", "")
 TYPE("swiftsourceinfo",     SwiftSourceInfoFile,       "swiftsourceinfo", "")
 TYPE("assembly",            Assembly,                  "s",               "")
 TYPE("raw-sil",             RawSIL,                    "sil",             "")
+TYPE("lowered-sil",         LoweredSIL,                "sil",             "")
 TYPE("raw-sib",             RawSIB,                    "sib",             "")
 TYPE("llvm-ir",             LLVM_IR,                   "ll",              "")
 TYPE("raw-llvm-ir",         RawLLVM_IR,                "ll",              "")

include/swift/Frontend/FrontendOptions.h

@@ -182,20 +182,21 @@ public:
     Immediate, ///< Immediate mode
     REPL,      ///< REPL mode
 
-    EmitAssembly, ///< Emit assembly
+    EmitAssembly,   ///< Emit assembly
-    EmitIRGen,    ///< Emit LLVM IR before LLVM optimizations
+    EmitLoweredSIL, ///< Emit lowered SIL before IRGen runs
-    EmitIR,       ///< Emit LLVM IR after LLVM optimizations
+    EmitIRGen,      ///< Emit LLVM IR before LLVM optimizations
-    EmitBC,       ///< Emit LLVM BC
+    EmitIR,         ///< Emit LLVM IR after LLVM optimizations
-    EmitObject,   ///< Emit object file
+    EmitBC,         ///< Emit LLVM BC
+    EmitObject,     ///< Emit object file
 
     DumpTypeInfo, ///< Dump IRGen type info
 
     EmitPCM, ///< Emit precompiled Clang module from a module map
     DumpPCM, ///< Dump information about a precompiled Clang module
 
-    ScanDependencies,        ///< Scan dependencies of Swift source files
+    ScanDependencies, ///< Scan dependencies of Swift source files
-    PrintVersion,       ///< Print version information.
+    PrintVersion,     ///< Print version information.
-    PrintFeature,       ///< Print supported feature of this compiler
+    PrintFeature,     ///< Print supported feature of this compiler
   };
 
   /// Indicates the action the user requested that the frontend perform.

include/swift/Option/Options.td

@@ -1287,6 +1287,8 @@ def emit_sil : Flag<["-"], "emit-sil">,
   HelpText<"Emit canonical SIL file(s)">, ModeOpt;
 def emit_silgen : Flag<["-"], "emit-silgen">,
   HelpText<"Emit raw SIL file(s)">, ModeOpt;
+def emit_lowered_sil : Flag<["-"], "emit-lowered-sil">,
+  HelpText<"Emit lowered SIL file(s)">, ModeOpt;
 def emit_sib : Flag<["-"], "emit-sib">,
   HelpText<"Emit serialized AST + canonical SIL file(s)">, ModeOpt;
 def emit_sibgen : Flag<["-"], "emit-sibgen">,

lib/Basic/FileTypes.cpp

@@ -93,6 +93,7 @@ bool file_types::isTextual(ID Id) {
   switch (Id) {
   case file_types::TY_Swift:
   case file_types::TY_SIL:
+  case file_types::TY_LoweredSIL:
   case file_types::TY_Dependencies:
   case file_types::TY_Assembly:
   case file_types::TY_ASTDump:
@@ -160,6 +161,7 @@ bool file_types::isAfterLLVM(ID Id) {
   case file_types::TY_ImportedModules:
   case file_types::TY_TBD:
   case file_types::TY_SIL:
+  case file_types::TY_LoweredSIL:
   case file_types::TY_Dependencies:
   case file_types::TY_ASTDump:
   case file_types::TY_RawSIL:
@@ -211,6 +213,7 @@ bool file_types::isPartOfSwiftCompilation(ID Id) {
   switch (Id) {
   case file_types::TY_Swift:
   case file_types::TY_SIL:
+  case file_types::TY_LoweredSIL:
   case file_types::TY_RawSIL:
   case file_types::TY_SIB:
   case file_types::TY_RawSIB:
@@ -274,6 +277,7 @@ bool file_types::isProducedFromDiagnostics(ID Id) {
     return true;
   case file_types::TY_Swift:
   case file_types::TY_SIL:
+  case file_types::TY_LoweredSIL:
   case file_types::TY_RawSIL:
   case file_types::TY_SIB:
   case file_types::TY_RawSIB:

lib/Driver/Driver.cpp

@@ -1160,6 +1160,10 @@ void Driver::buildOutputInfo(const ToolChain &TC, const DerivedArgList &Args,
       OI.CompilerOutputType = file_types::TY_RawSIL;
       break;
 
+    case options::OPT_emit_lowered_sil:
+      OI.CompilerOutputType = file_types::TY_LoweredSIL;
+      break;
+
     case options::OPT_emit_sib:
       OI.CompilerOutputType = file_types::TY_SIB;
       break;
@@ -1619,6 +1623,7 @@ void Driver::buildActions(SmallVectorImpl<const Action *> &TopLevelActions,
       switch (InputType) {
       case file_types::TY_Swift:
       case file_types::TY_SIL:
+      case file_types::TY_LoweredSIL:
       case file_types::TY_SIB: {
         // Source inputs always need to be compiled.
         assert(file_types::isPartOfSwiftCompilation(InputType));

lib/Driver/ToolChains.cpp

@@ -708,6 +708,8 @@ const char *ToolChain::JobContext::computeFrontendModeForCompile() const {
     return "-emit-silgen";
   case file_types::TY_SIL:
     return "-emit-sil";
+  case file_types::TY_LoweredSIL:
+    return "-emit-lowered-sil";
   case file_types::TY_RawSIB:
     return "-emit-sibgen";
   case file_types::TY_SIB:
@@ -1008,6 +1010,7 @@ ToolChain::constructInvocation(const BackendJobAction &job,
     case file_types::TY_RawSIL:
     case file_types::TY_RawSIB:
     case file_types::TY_SIL:
+    case file_types::TY_LoweredSIL:
     case file_types::TY_SIB:
     case file_types::TY_PCH:
     case file_types::TY_ClangModuleFile:

lib/Frontend/ArgsToFrontendOptionsConverter.cpp

@@ -547,6 +547,8 @@ ArgsToFrontendOptionsConverter::determineRequestedAction(const ArgList &args) {
     return FrontendOptions::ActionType::EmitSIL;
   if (Opt.matches(OPT_emit_silgen))
     return FrontendOptions::ActionType::EmitSILGen;
+  if (Opt.matches(OPT_emit_lowered_sil))
+    return FrontendOptions::ActionType::EmitLoweredSIL;
   if (Opt.matches(OPT_emit_sib))
     return FrontendOptions::ActionType::EmitSIB;
   if (Opt.matches(OPT_emit_sibgen))

lib/Frontend/FrontendOptions.cpp

@@ -47,6 +47,7 @@ bool FrontendOptions::needsProperModuleName(ActionType action) {
     return false;
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitModuleOnly:
@@ -113,6 +114,7 @@ bool FrontendOptions::doesActionRequireSwiftStandardLibrary(ActionType action) {
   case ActionType::DumpTypeRefinementContexts:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitModuleOnly:
   case ActionType::MergeModules:
   case ActionType::EmitSIBGen:
@@ -158,6 +160,7 @@ bool FrontendOptions::doesActionRequireInputs(ActionType action) {
   case ActionType::DumpTypeRefinementContexts:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitModuleOnly:
   case ActionType::MergeModules:
   case ActionType::EmitSIBGen:
@@ -200,6 +203,7 @@ bool FrontendOptions::doesActionPerformEndOfPipelineActions(ActionType action) {
   case ActionType::DumpTypeRefinementContexts:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitModuleOnly:
   case ActionType::MergeModules:
   case ActionType::EmitSIBGen:
@@ -252,6 +256,7 @@ bool FrontendOptions::supportCompilationCaching(ActionType action) {
   case ActionType::EmitObject:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitModuleOnly:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
@@ -315,6 +320,9 @@ FrontendOptions::formatForPrincipalOutputFileForAction(ActionType action) {
   case ActionType::EmitSIL:
     return TY_SIL;
 
+  case ActionType::EmitLoweredSIL:
+    return TY_LoweredSIL;
+
   case ActionType::EmitSIBGen:
     return TY_RawSIB;
 
@@ -387,6 +395,7 @@ bool FrontendOptions::canActionEmitDependencies(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -431,6 +440,7 @@ bool FrontendOptions::canActionEmitReferenceDependencies(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -475,6 +485,7 @@ bool FrontendOptions::canActionEmitModuleSummary(ActionType action) {
   case ActionType::PrintFeature:
     return false;
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
   case ActionType::EmitIR:
@@ -515,6 +526,7 @@ bool FrontendOptions::canActionEmitClangHeader(ActionType action) {
   case ActionType::EmitModuleOnly:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -557,6 +569,7 @@ bool FrontendOptions::canActionEmitLoadedModuleTrace(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -599,6 +612,7 @@ bool FrontendOptions::canActionEmitModuleSemanticInfo(ActionType action) {
   case ActionType::PrintVersion:
   case ActionType::PrintFeature:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -647,6 +661,7 @@ bool FrontendOptions::canActionEmitConstValues(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -688,6 +703,7 @@ bool FrontendOptions::canActionEmitModule(ActionType action) {
   case ActionType::MergeModules:
   case ActionType::EmitModuleOnly:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
@@ -735,6 +751,7 @@ bool FrontendOptions::canActionEmitInterface(ActionType action) {
   case ActionType::MergeModules:
   case ActionType::EmitModuleOnly:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
   case ActionType::EmitIR:
@@ -777,6 +794,7 @@ bool FrontendOptions::canActionEmitAPIDescriptor(ActionType action) {
   case ActionType::MergeModules:
   case ActionType::EmitModuleOnly:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIB:
   case ActionType::EmitIRGen:
   case ActionType::EmitIR:
@@ -804,6 +822,7 @@ bool FrontendOptions::doesActionProduceOutput(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitModuleOnly:
@@ -862,6 +881,7 @@ bool FrontendOptions::doesActionProduceTextualOutput(ActionType action) {
   case ActionType::EmitImportedModules:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitAssembly:
   case ActionType::EmitIRGen:
   case ActionType::EmitIR:
@@ -901,6 +921,7 @@ bool FrontendOptions::doesActionGenerateSIL(ActionType action) {
   case ActionType::EmitSILGen:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIB:
   case ActionType::EmitModuleOnly:
   case ActionType::MergeModules:
@@ -938,6 +959,7 @@ bool FrontendOptions::doesActionGenerateIR(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitImportedModules:
@@ -981,6 +1003,7 @@ bool FrontendOptions::doesActionBuildModuleFromInterface(ActionType action) {
   case ActionType::EmitPCH:
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
+  case ActionType::EmitLoweredSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
   case ActionType::EmitImportedModules:

lib/FrontendTool/FrontendTool.cpp

@@ -1279,6 +1279,7 @@ static bool performAction(CompilerInstance &Instance,
   case FrontendOptions::ActionType::EmitSILGen:
   case FrontendOptions::ActionType::EmitSIBGen:
   case FrontendOptions::ActionType::EmitSIL:
+  case FrontendOptions::ActionType::EmitLoweredSIL:
   case FrontendOptions::ActionType::EmitSIB:
   case FrontendOptions::ActionType::EmitModuleOnly:
   case FrontendOptions::ActionType::MergeModules:
@@ -1748,6 +1749,10 @@ static bool performCompileStepsPostSILGen(CompilerInstance &Instance,
 
   runSILLoweringPasses(*SM);
 
+  // If we are asked to emit lowered SIL, dump it now and return.
+  if (Action == FrontendOptions::ActionType::EmitLoweredSIL)
+    return writeSIL(*SM, PSPs, Instance, Invocation.getSILOptions());
+
   // Cancellation check after SILLowering.
   if (Instance.isCancellationRequested())
     return true;

test/Frontend/lowered_sil.swift

@@ -0,0 +1,6 @@
+// RUN: %target-swift-frontend -o - -emit-lowered-sil %s | %FileCheck %s
+
+// CHECK: sil_stage lowered
+
+func test() {
+}

unittests/Basic/FileTypes.cpp

@@ -27,9 +27,10 @@ TEST(FileSystem, lookupTypeFromFilename) {
     // no extension, skip.
     if (Entry.first.empty())
       continue;
-    // raw-sil, raw-sib, and raw-llvm-ir do not have unique extensions.
+    // raw-sil, raw-sib, lowered-sil, and raw-llvm-ir do not have unique
+    // extensions.
     if (Entry.second == TY_RawSIL || Entry.second == TY_RawSIB ||
-        Entry.second == TY_RawLLVM_IR)
+        Entry.second == TY_LoweredSIL || Entry.second == TY_RawLLVM_IR)
       continue;
 
     std::string Filename = "Myfile." + Entry.first;