averello/swift-mirror
1
0
Fork 0
mirror of https://github.com/apple/swift.git synced 2025-12-14 20:36:38 +01:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #85499 from cachemeifyoucan/eng/PR-164409895

Browse Source 
[Caching] Fix multi-threaded WMO with MCCAS
This commit is contained in:
Steven Wu
2025-11-18 09:22:13 -08:00
committed by GitHub
parent 5c3a26633a b1d669bea1
commit b56f541732
9 changed files with 158 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
include/swift/AST/IRGenRequests.h
View File

@@ -33,6 +33,10 @@ class SILOptions;
struct TBDGenOptions;
class TBDGenDescriptor;
namespace cas {
class SwiftCASOutputBackend;
}
namespace irgen {
class IRGenModule;
}
@@ -149,12 +153,15 @@ struct IRGenDescriptor {
StringRef ModuleName;
const PrimarySpecificPaths &PSPs;
std::shared_ptr<llvm::cas::ObjectStore> CAS;
StringRef PrivateDiscriminator;
ArrayRef<std::string> parallelOutputFilenames;
ArrayRef<std::string> parallelIROutputFilenames;
llvm::GlobalVariable **outModuleHash;
swift::cas::SwiftCASOutputBackend *casBackend = nullptr;
llvm::raw_pwrite_stream *out = nullptr;
friend llvm::hash_code hash_value(const IRGenDescriptor &owner) {
return llvm::hash_combine(owner.Ctx, owner.SymbolsToEmit, owner.SILMod);
}
@@ -176,8 +183,10 @@ public:
const TBDGenOptions &TBDOpts, const SILOptions &SILOpts,
Lowering::TypeConverter &Conv, std::unique_ptr<SILModule> &&SILMod,
StringRef ModuleName, const PrimarySpecificPaths &PSPs,
std::shared_ptr<llvm::cas::ObjectStore> CAS,
StringRef PrivateDiscriminator, SymsToEmit symsToEmit = std::nullopt,
llvm::GlobalVariable **outModuleHash = nullptr) {
llvm::GlobalVariable **outModuleHash = nullptr,
cas::SwiftCASOutputBackend *casBackend = nullptr) {
return IRGenDescriptor{file,
symsToEmit,
Opts,
@@ -187,20 +196,26 @@ public:
SILMod.release(),
ModuleName,
PSPs,
std::move(CAS),
PrivateDiscriminator,
{},
{},
outModuleHash};
outModuleHash,
casBackend};
}
static IRGenDescriptor forWholeModule(
ModuleDecl *M, const IRGenOptions &Opts, const TBDGenOptions &TBDOpts,
const SILOptions &SILOpts, Lowering::TypeConverter &Conv,
std::unique_ptr<SILModule> &&SILMod, StringRef ModuleName,
const PrimarySpecificPaths &PSPs, SymsToEmit symsToEmit = std::nullopt,
ArrayRef<std::string> parallelOutputFilenames = {},
ArrayRef<std::string> parallelIROutputFilenames = {},
llvm::GlobalVariable **outModuleHash = nullptr) {
static IRGenDescriptor
forWholeModule(ModuleDecl *M, const IRGenOptions &Opts,
const TBDGenOptions &TBDOpts, const SILOptions &SILOpts,
Lowering::TypeConverter &Conv,
std::unique_ptr<SILModule> &&SILMod, StringRef ModuleName,
const PrimarySpecificPaths &PSPs,
std::shared_ptr<llvm::cas::ObjectStore> CAS,
SymsToEmit symsToEmit = std::nullopt,
ArrayRef<std::string> parallelOutputFilenames = {},
ArrayRef<std::string> parallelIROutputFilenames = {},
llvm::GlobalVariable **outModuleHash = nullptr,
cas::SwiftCASOutputBackend *casBackend = nullptr) {
return IRGenDescriptor{M,
symsToEmit,
Opts,
@@ -210,10 +225,12 @@ public:
SILMod.release(),
ModuleName,
PSPs,
std::move(CAS),
"",
parallelOutputFilenames,
parallelIROutputFilenames,
outModuleHash};
outModuleHash,
casBackend};
}
/// Retrieves the files to perform IR generation for. If the descriptor is

24
include/swift/Subsystems.h
View File

@@ -80,6 +80,10 @@ namespace swift {
class TypeConverter;
}
namespace cas {
class SwiftCASOutputBackend;
}
namespace fine_grained_dependencies {
class SourceFileDepGraph;
}
@@ -243,7 +247,8 @@ namespace swift {
/// Get the CPU, subtarget feature options, and triple to use when emitting code.
std::tuple<llvm::TargetOptions, std::string, std::vector<std::string>,
std::string>
getIRTargetOptions(const IRGenOptions &Opts, ASTContext &Ctx);
getIRTargetOptions(const IRGenOptions &Opts, ASTContext &Ctx,
std::shared_ptr<llvm::cas::ObjectStore> CAS = nullptr);
/// Turn the given Swift module into LLVM IR and return the generated module.
/// To compile and output the generated code, call \c performLLVM.
@@ -252,19 +257,23 @@ namespace swift {
const TBDGenOptions &TBDOpts,
std::unique_ptr<SILModule> SILMod, StringRef ModuleName,
const PrimarySpecificPaths &PSPs,
std::shared_ptr<llvm::cas::ObjectStore> CAS,
ArrayRef<std::string> parallelOutputFilenames,
ArrayRef<std::string> parallelIROutputFilenames,
llvm::GlobalVariable **outModuleHash = nullptr);
llvm::GlobalVariable **outModuleHash = nullptr,
cas::SwiftCASOutputBackend *casBackend = nullptr);
/// Turn the given Swift file into LLVM IR and return the generated module.
/// To compile and output the generated code, call \c performLLVM.
GeneratedModule
performIRGeneration(FileUnit *file, const IRGenOptions &Opts,
performIRGeneration(FileUnit *file, const IRGenOptions &Opts,
const TBDGenOptions &TBDOpts,
std::unique_ptr<SILModule> SILMod,
StringRef ModuleName, const PrimarySpecificPaths &PSPs,
std::unique_ptr<SILModule> SILMod, StringRef ModuleName,
const PrimarySpecificPaths &PSPs,
std::shared_ptr<llvm::cas::ObjectStore> CAS,
StringRef PrivateDiscriminator,
llvm::GlobalVariable **outModuleHash = nullptr);
llvm::GlobalVariable **outModuleHash = nullptr,
cas::SwiftCASOutputBackend *casBackend = nullptr);
/// Given an already created LLVM module, construct a pass pipeline and run
/// the Swift LLVM Pipeline upon it. This will include the emission of LLVM IR
@@ -330,7 +339,8 @@ namespace swift {
/// Creates a TargetMachine from the IRGen opts and AST Context.
std::unique_ptr<llvm::TargetMachine>
createTargetMachine(const IRGenOptions &Opts, ASTContext &Ctx);
createTargetMachine(const IRGenOptions &Opts, ASTContext &Ctx,
std::shared_ptr<llvm::cas::ObjectStore> CAS);
/// A convenience wrapper for Parser functionality.
class ParserUnit {