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[Serialization] Use existing logic to print a hierarchical module name

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No intended functionality change.
This commit is contained in:
Jordan Rose
2019-08-19 16:29:21 -07:00
parent 12fc3537a8
commit c6f033d400
3 changed files with 11 additions and 14 deletions
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5
lib/AST/Module.cpp
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@@ -1200,11 +1200,12 @@ ModuleDecl::ReverseFullNameIterator::operator++() {
}
void
ModuleDecl::ReverseFullNameIterator::printForward(raw_ostream &out) const {
ModuleDecl::ReverseFullNameIterator::printForward(raw_ostream &out,
StringRef delim) const {
SmallVector<StringRef, 8> elements(*this, {});
swift::interleave(swift::reversed(elements),
[&out](StringRef next) { out << next; },
[&out] { out << '.'; });
[&out, delim] { out << delim; });
}
void