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20c5dff4b5
TLDR: This patch introduces a new kind of builtin, "a polymorphic builtin". One calls it like any other builtin, e.x.: ``` Builtin.generic_add(x, y) ``` but it has a contract: it must be specialized to a concrete builtin by the time we hit Lowered SIL. In this commit, I add support for the following generic operations: Type | Op ------------------------ FloatOrVector |FAdd FloatOrVector |FDiv FloatOrVector |FMul FloatOrVector |FRem FloatOrVector |FSub IntegerOrVector|AShr IntegerOrVector|Add IntegerOrVector|And IntegerOrVector|ExactSDiv IntegerOrVector|ExactUDiv IntegerOrVector|LShr IntegerOrVector|Mul IntegerOrVector|Or IntegerOrVector|SDiv IntegerOrVector|SRem IntegerOrVector|Shl IntegerOrVector|Sub IntegerOrVector|UDiv IntegerOrVector|Xor Integer |URem NOTE: I only implemented support for the builtins in SIL and in SILGen. I am going to implement the optimizer parts of this in a separate series of commits. DISCUSSION ---------- Today there are polymorphic like instructions in LLVM-IR. Yet, at the swift and SIL level we represent these operations instead as Builtins whose names are resolved by splatting the builtin into the name. For example, adding two things in LLVM: ``` %2 = add i64 %0, %1 %2 = add <2 x i64> %0, %1 %2 = add <4 x i64> %0, %1 %2 = add <8 x i64> %0, %1 ``` Each of the add operations are done by the same polymorphic instruction. In constrast, we splat out these Builtins in swift today, i.e.: ``` let x, y: Builtin.Int32 Builtin.add_Int32(x, y) let x, y: Builtin.Vec4xInt32 Builtin.add_Vec4xInt32(x, y) ... ``` In SIL, we translate these verbatim and then IRGen just lowers them to the appropriate polymorphic instruction. Beyond being verbose, these prevent these Builtins (which need static types) from being used in polymorphic contexts where we can guarantee that eventually a static type will be provided. In contrast, the polymorphic builtins introduced in this commit can be passed any type, with the proviso that the expert user using this feature can guarantee that before we reach Lowered SIL, the generic_add has been eliminated. This is enforced by IRGen asserting if passed such a builtin and by the SILVerifier checking that the underlying builtin is never called once the module is in Lowered SIL. In forthcoming commits, I am going to add two optimizations that give the stdlib tool writer the tools needed to use this builtin: 1. I am going to add an optimization to constant propagation that changes a "generic_*" op to the type of its argument if the argument is a type that is valid for the builtin (i.e. integer or vector). 2. I am going to teach the SILCloner how to specialize these as it inlines. This ensures that when we transparent inline, we specialize the builtin automatically and can then form SSA at -Onone using predictable memory access operations. The main implication around these polymorphic builtins are that if an author is not able to specialize the builtin, they need to ensure that after constant propagation, the generic builtin has been DCEed. The general rules are that the -Onone optimizer will constant fold branches with constant integer operands. So if one can use a bool of some sort to trigger the operation, one can be guaranteed that the code will not codegen. I am considering putting in some sort of diagnostic to ensure that the stdlib writer has a good experience (e.x. get an error instead of crashing the compiler).
136 lines
7.0 KiB
Plaintext
136 lines
7.0 KiB
Plaintext
// RUN: %target-sil-opt %s -o - | %target-sil-opt
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// Just make sure we can parse polymorphic builtins, recognize them, round trip
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// them.
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sil_stage raw
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import Builtin
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sil @generic_add_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_add"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_add_indirect_param_test : $@convention(thin) (@in Builtin.Vec4xInt32, @in Builtin.Vec4xInt32) -> @out Builtin.Vec4xInt32 {
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bb0(%0 : $*Builtin.Vec4xInt32, %1 : $*Builtin.Vec4xInt32, %2 : $*Builtin.Vec4xInt32):
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%3 = builtin "generic_add"<Builtin.Vec4xInt32>(%0 : $*Builtin.Vec4xInt32, %1 : $*Builtin.Vec4xInt32, %2 : $*Builtin.Vec4xInt32) : $()
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%9999 = tuple()
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return %9999 : $()
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}
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sil @generic_fadd_test : $@convention(thin) (Builtin.Vec4xFPIEEE32, Builtin.Vec4xFPIEEE32) -> Builtin.Vec4xFPIEEE32 {
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bb0(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32):
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%2 = builtin "generic_fadd"<Builtin.Vec4xFPIEEE32>(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32) : $Builtin.Vec4xFPIEEE32
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return %2 : $Builtin.Vec4xFPIEEE32
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}
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sil @generic_and_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_and"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_ashr_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_ashr"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_lshr_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_lshr"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_or_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_or"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_fdiv_test : $@convention(thin) (Builtin.Vec4xFPIEEE32, Builtin.Vec4xFPIEEE32) -> Builtin.Vec4xFPIEEE32 {
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bb0(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32):
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%2 = builtin "generic_fdiv"<Builtin.Vec4xFPIEEE32>(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32) : $Builtin.Vec4xFPIEEE32
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return %2 : $Builtin.Vec4xFPIEEE32
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}
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sil @generic_mul_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_mul"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_fmul_test : $@convention(thin) (Builtin.Vec4xFPIEEE32, Builtin.Vec4xFPIEEE32) -> Builtin.Vec4xFPIEEE32 {
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bb0(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32):
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%2 = builtin "generic_fmul"<Builtin.Vec4xFPIEEE32>(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32) : $Builtin.Vec4xFPIEEE32
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return %2 : $Builtin.Vec4xFPIEEE32
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}
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sil @generic_sdiv_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_sdiv"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_sdiv_exact_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_sdiv_exact"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_shl_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_shl"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_srem_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_srem"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_sub_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_sub"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_udiv_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_udiv"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_udiv_exact_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_udiv_exact"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_xor_test : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "generic_xor"<Builtin.Vec4xInt32>(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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sil @generic_fsub_test : $@convention(thin) (Builtin.Vec4xFPIEEE32, Builtin.Vec4xFPIEEE32) -> Builtin.Vec4xFPIEEE32 {
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bb0(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32):
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%2 = builtin "generic_fsub"<Builtin.Vec4xFPIEEE32>(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32) : $Builtin.Vec4xFPIEEE32
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return %2 : $Builtin.Vec4xFPIEEE32
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}
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sil @generic_frem_test : $@convention(thin) (Builtin.Vec4xFPIEEE32, Builtin.Vec4xFPIEEE32) -> Builtin.Vec4xFPIEEE32 {
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bb0(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32):
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%2 = builtin "generic_frem"<Builtin.Vec4xFPIEEE32>(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32) : $Builtin.Vec4xFPIEEE32
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return %2 : $Builtin.Vec4xFPIEEE32
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}
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sil @generic_urem_test : $@convention(thin) (Builtin.Int64, Builtin.Int64) -> Builtin.Int64 {
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bb0(%0 : $Builtin.Int64, %1 : $Builtin.Int64):
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%2 = builtin "generic_urem"<Builtin.Int64>(%0 : $Builtin.Int64, %1 : $Builtin.Int64) : $Builtin.Int64
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return %2 : $Builtin.Int64
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}
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