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29 lines
1.4 KiB
Plaintext
29 lines
1.4 KiB
Plaintext
// RUN: %target-swift-frontend -emit-ir -parse-sil %s -module-name Swift -parse-stdlib | %FileCheck %s
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// This file provides examples on how vector computations are written at the SIL
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// level and how they are translated by IRGen to LLVM IR intrinsics.
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import Builtin
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// CHECK-LABEL: define{{( protected| dllexport)?}} swiftcc <4 x i32> @vector_int_add(<4 x i32> %0, <4 x i32> %1) {{.*}} {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: %2 = add <4 x i32> %0, %1
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// CHECK-NEXT: ret <4 x i32> %2
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// CHECK-NEXT: }
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sil @vector_int_add : $@convention(thin) (Builtin.Vec4xInt32, Builtin.Vec4xInt32) -> Builtin.Vec4xInt32 {
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bb0(%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32):
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%2 = builtin "add_Vec4xInt32" (%0 : $Builtin.Vec4xInt32, %1 : $Builtin.Vec4xInt32) : $Builtin.Vec4xInt32
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return %2 : $Builtin.Vec4xInt32
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}
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// CHECK-LABEL: define{{( protected| dllexport)?}} swiftcc <4 x float> @vector_float_add(<4 x float> %0, <4 x float> %1) {{.*}} {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: %2 = fadd <4 x float> %0, %1
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// CHECK-NEXT: ret <4 x float> %2
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// CHECK-NEXT: }
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sil @vector_float_add : $@convention(thin) (Builtin.Vec4xFPIEEE32, Builtin.Vec4xFPIEEE32) -> Builtin.Vec4xFPIEEE32 {
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bb0(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32):
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%2 = builtin "fadd_Vec4xFPIEEE32"(%0 : $Builtin.Vec4xFPIEEE32, %1 : $Builtin.Vec4xFPIEEE32) : $Builtin.Vec4xFPIEEE32
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return %2 : $Builtin.Vec4xFPIEEE32
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}
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