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592d72bba9
WIP to add more overloads to optimize SIMD codegen on concrete types. Here we do: - init(repeating:) - init(lowHalf:highHalf:) These are always inlined, even in debug, since LLVM knows how to lower them to one or two instructions on the targets that we care about.
85 lines
3.5 KiB
Swift
85 lines
3.5 KiB
Swift
//===--- SIMDMaskInitializers.swift.gyb -------------------*- swift -*-===//
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//
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// This source file is part of the Swift.org open source project
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//
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// Copyright (c) 2025 Apple Inc. and the Swift project authors
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// Licensed under Apache License v2.0 with Runtime Library Exception
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//
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// See https://swift.org/LICENSE.txt for license information
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// See https://swift.org/CONTRIBUTORS.txt for the list of Swift project authors
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//
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//===----------------------------------------------------------------------===//
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// RUN: %empty-directory(%t)
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// RUN: %gyb %s -o %t/SIMDMaskInitializers.swift
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// RUN: %target-swift-frontend -primary-file %t/SIMDMaskInitializers.swift -S | %FileCheck %t/SIMDMaskInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKOnone-%target-cpu
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// RUN: %target-swift-frontend -primary-file %t/SIMDMaskInitializers.swift -S -O | %FileCheck %t/SIMDMaskInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKO-%target-cpu
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import Swift
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%for bits in [8,16,32,64]:
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% for totalBits in [64,128]:
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% n = totalBits // bits
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% if n != 1:
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% neonSuffix = str(n) + {8:'b',16:'h',32:'s',64:'d'}[bits]
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func repeating${n}_mask${bits}(_ scalar: Bool) -> SIMDMask<SIMD${n}<Int${bits}>> {
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SIMDMask(repeating: scalar)
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}
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// CHECK: repeating${n}_mask${bits}{{[[:alnum:]]+}}:
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// CHECKO-arm64-NEXT: sbfx [[REG:[wx][0-9]]], {{[wx]}}0, #0, #1
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// CHECKO-arm64-NEXT: dup.${neonSuffix} v0, [[REG]]
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// CHECKO-arm64-NEXT: ret
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// CHECKOnone-arm64: dup.${neonSuffix}
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// CHECKOnone-arm64: ret
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% end
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% end
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%end
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func concat8x8(_ a: SIMDMask<SIMD8<Int8>>, _ b: SIMDMask<SIMD8<Int8>>) -> SIMDMask<SIMD16<Int8>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers9concat8x8ys0A0Vys6SIMD16Vys4Int8VGGADys5SIMD8VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
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// CHECKO-arm64-NEXT: ret
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// CHECKO-x86_64: punpcklqdq
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func concat16x8(_ a: SIMDMask<SIMD16<Int8>>, _ b: SIMDMask<SIMD16<Int8>>) -> SIMDMask<SIMD32<Int8>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers10concat16x8ys0A0Vys6SIMD32Vys4Int8VGGADys6SIMD16VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: ret
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func concat4x16(_ a: SIMDMask<SIMD4<Int16>>, _ b: SIMDMask<SIMD4<Int16>>) -> SIMDMask<SIMD8<Int16>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers10concat4x16ys0A0Vys5SIMD8Vys5Int16VGGADys5SIMD4VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
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// CHECKO-arm64-NEXT: ret
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// CHECKO-x86_64: punpcklqdq
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func concat8x16(_ a: SIMDMask<SIMD8<Int16>>, _ b: SIMDMask<SIMD8<Int16>>) -> SIMDMask<SIMD16<Int16>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers10concat8x16ys0A0Vys6SIMD16Vys5Int16VGGADys5SIMD8VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: ret
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func concat2x32(_ a: SIMDMask<SIMD2<Int32>>, _ b: SIMDMask<SIMD2<Int32>>) -> SIMDMask<SIMD4<Int32>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers10concat2x32ys0A0Vys5SIMD4Vys5Int32VGGADys5SIMD2VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
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// CHECKO-arm64-NEXT: ret
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// CHECKO-x86_64: punpcklqdq
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func concat4x32(_ a: SIMDMask<SIMD4<Int32>>, _ b: SIMDMask<SIMD4<Int32>>) -> SIMDMask<SIMD8<Int32>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers10concat4x32ys0A0Vys5SIMD8Vys5Int32VGGADys5SIMD4VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: ret
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func concat2x64(_ a: SIMDMask<SIMD2<Int64>>, _ b: SIMDMask<SIMD2<Int64>>) -> SIMDMask<SIMD4<Int64>> {
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SIMDMask(lowHalf: a, highHalf: b)
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}
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// CHECK: s20SIMDMaskInitializers10concat2x64ys0A0Vys5SIMD4Vys5Int64VGGADys5SIMD2VyAHGG_ANtF:
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// CHECKO-arm64-NEXT: ret
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