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This patch fixes a number of issues: The analysis was using EpilogueARCContext as a temporary when computing. This is an performance problem since EpilogueARCContext contains all of the memory used in the analysis. So essentially, we were mallocing tons of memory every time we missed the analyses cache. This patch changes the pass to instead have 1 EpilogueARCContext whose internal state is cleared in between invocations. Since the data structures (see below) used after this patch do not shrink memory after being cleared, this should cause us to have far less memory churn. The analysis was managing its block state data structure by allocating the individual block state structs using a BumpPtrAllocator/DenseMap stored in EpilogueARCContext. The individual state structures were allocated from the BumpPtrAllocator and the DenseMap then mapped a specific SILBasicBlock to its State data structure. Ignoring that we were mallocing this memory every time we computed rather than reusing global state, this pessimizes performance on small functions significantly. This is because the BumpPtrAllocator by default heap allocates initially a page and DenseMap initially mallocs a 64 entry hash table. Thus for a 1 block function, we would be allocating a large amount of memory that is just unneeded. Instead this patch changes the analysis to use a std::vector in combination with PostOrderFunctionInfo to manage the per block state. The way this works is that PostOrderFunctionInfo already contains a map from a SILBasicBlock to its post order number. So, when we are allocating memory for each block, we visit the CFG in post order. Thus we know that each block's state will be stored in the vector at vector[post order number]. This has a number of nice effects: 1. By eliminating the need for the DenseMap, in large test cases, we are signficiantly reducing the memory overhead (by 24 bytes per basic block assuming 8 byte ptrs). 2. We will use far less memory when applying this analysis to small functions. rdar://33841629
175 lines
6.1 KiB
C++
175 lines
6.1 KiB
C++
//===--- EpilogueARCAnalysis.cpp ------------------------------------------===//
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//
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// This source file is part of the Swift.org open source project
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//
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// Copyright (c) 2014 - 2017 Apple Inc. and the Swift project authors
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// Licensed under Apache License v2.0 with Runtime Library Exception
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//
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// See https://swift.org/LICENSE.txt for license information
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// See https://swift.org/CONTRIBUTORS.txt for the list of Swift project authors
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//
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//===----------------------------------------------------------------------===//
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#include "swift/SILOptimizer/Analysis/EpilogueARCAnalysis.h"
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#include "swift/SILOptimizer/Analysis/DominanceAnalysis.h"
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#include "swift/SIL/SILInstruction.h"
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#include "llvm/Support/CommandLine.h"
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using namespace swift;
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//===----------------------------------------------------------------------===//
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// Epilogue ARC Utilities
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//===----------------------------------------------------------------------===//
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void EpilogueARCContext::initializeDataflow() {
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for (auto *BB : PO->getPostOrder()) {
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// Find the exit blocks.
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if (isInterestedFunctionExitingBlock(BB)) {
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ExitBlocks.insert(BB);
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}
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// Allocate state for this block.
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IndexToStateMap.emplace_back();
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}
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// Split the SILArgument into local arguments to each specific basic block.
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llvm::SmallVector<SILValue, 4> ToProcess;
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llvm::DenseSet<SILValue> Processed;
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ToProcess.push_back(Arg);
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while (!ToProcess.empty()) {
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SILValue CArg = ToProcess.pop_back_val();
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if (!CArg)
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continue;
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if (Processed.find(CArg) != Processed.end())
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continue;
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Processed.insert(CArg);
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if (auto *A = dyn_cast<SILPHIArgument>(CArg)) {
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// Find predecessor and break the SILArgument to predecessors.
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for (auto *X : A->getParent()->getPredecessorBlocks()) {
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// Try to find the predecessor edge-value.
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SILValue IA = A->getIncomingValue(X);
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getState(X).LocalArg = IA;
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// Maybe the edge value is another SILArgument.
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ToProcess.push_back(IA);
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}
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}
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}
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}
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bool EpilogueARCContext::convergeDataflow() {
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// Keep iterating until Changed is false.
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bool Changed = false;
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do {
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Changed = false;
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// Iterate until the data flow converges.
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for (SILBasicBlock *B : PO->getPostOrder()) {
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auto &BS = getState(B);
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// Merge in all the successors.
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bool BBSetOut = false;
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if (!B->succ_empty()) {
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auto Iter = B->succ_begin();
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BBSetOut = getState(*Iter).BBSetIn;
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Iter = std::next(Iter);
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for (auto E = B->succ_end(); Iter != E; ++Iter) {
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BBSetOut &= getState(*Iter).BBSetIn;
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}
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} else if (isExitBlock(B)) {
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// We set the BBSetOut for exit blocks.
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BBSetOut = true;
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}
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// If an epilogue ARC instruction or blocking operating has been identified
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// then there is no point visiting every instruction in this block.
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if (BBSetOut) {
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// Iterate over all instructions in the basic block and find the
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// interested ARC instruction in the block.
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for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
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// This is a transition from 1 to 0 due to an interested instruction.
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if (isInterestedInstruction(&*I)) {
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BBSetOut = false;
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break;
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}
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// This is a transition from 1 to 0 due to a blocking instruction.
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// at this point, its OK to abort the data flow as we have one path
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// which we did not find an epilogue retain before getting blocked.
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if (mayBlockEpilogueARC(&*I, RCFI->getRCIdentityRoot(Arg))) {
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return false;
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}
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}
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}
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// Update BBSetIn.
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Changed |= (BS.BBSetIn != BBSetOut);
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BS.BBSetIn = BBSetOut;
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}
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} while (Changed);
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return true;
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}
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bool EpilogueARCContext::computeEpilogueARC() {
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// At this point the data flow should have converged. Find the epilogue
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// releases.
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for (SILBasicBlock *B : PO->getPostOrder()) {
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bool BBSetOut = false;
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// Merge in all the successors.
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if (!B->succ_empty()) {
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// Make sure we've either found no ARC instructions in all the successors
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// or we've found ARC instructions in all successors.
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//
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// In case we've found ARC instructions in some and not all successors,
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// that means from this point to the end of the function, some paths will
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// not have an epilogue ARC instruction, which means the data flow has
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// failed.
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auto Iter = B->succ_begin();
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auto Base = getState(*Iter).BBSetIn;
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Iter = std::next(Iter);
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for (auto E = B->succ_end(); Iter != E; ++Iter) {
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if (getState(*Iter).BBSetIn != Base)
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return false;
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}
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BBSetOut = Base;
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} else if (isExitBlock(B)) {
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// We set the BBSetOut for exit blocks.
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BBSetOut = true;
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}
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// If an epilogue ARC instruction or blocking operating has been identified
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// then there is no point visiting every instruction in this block.
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if (!BBSetOut) {
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continue;
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}
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// An epilogue ARC instruction has not been identified, maybe its in this block.
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//
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// Iterate over all instructions in the basic block and find the interested ARC
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// instruction in the block.
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for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
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// This is a transition from 1 to 0 due to an interested instruction.
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if (isInterestedInstruction(&*I)) {
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EpilogueARCInsts.insert(&*I);
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break;
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}
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// This is a transition from 1 to 0 due to a blocking instruction.
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if (mayBlockEpilogueARC(&*I, RCFI->getRCIdentityRoot(Arg))) {
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break;
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}
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}
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}
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Main Entry Point
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//===----------------------------------------------------------------------===//
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void EpilogueARCAnalysis::initialize(SILPassManager *PM) {
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AA = PM->getAnalysis<AliasAnalysis>();
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PO = PM->getAnalysis<PostOrderAnalysis>();
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RC = PM->getAnalysis<RCIdentityAnalysis>();
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}
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SILAnalysis *swift::createEpilogueARCAnalysis(SILModule *M) {
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return new EpilogueARCAnalysis(M);
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}
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