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c026e95cce
This makes it easier to understand conceptually why a ValueOwnershipKind with Any ownership is invalid and also allowed me to explicitly document the lattice that relates ownership constraints/value ownership kinds.
381 lines
12 KiB
C++
381 lines
12 KiB
C++
//===--- BasicBlockUtils.cpp - Utilities for SILBasicBlock ----------------===//
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//
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// This source file is part of the Swift.org open source project
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//
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// Copyright (c) 2014 - 2017 Apple Inc. and the Swift project authors
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// Licensed under Apache License v2.0 with Runtime Library Exception
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//
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// See https://swift.org/LICENSE.txt for license information
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// See https://swift.org/CONTRIBUTORS.txt for the list of Swift project authors
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//
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//===----------------------------------------------------------------------===//
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#include "swift/SIL/BasicBlockUtils.h"
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#include "swift/SIL/Dominance.h"
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#include "swift/SIL/LoopInfo.h"
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#include "swift/SIL/SILArgument.h"
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#include "swift/SIL/SILBasicBlock.h"
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#include "swift/SIL/SILBuilder.h"
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#include "swift/SIL/SILFunction.h"
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#include "swift/SIL/TerminatorUtils.h"
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using namespace swift;
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static bool hasBranchArguments(TermInst *T, unsigned edgeIdx) {
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if (auto *BI = dyn_cast<BranchInst>(T)) {
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assert(edgeIdx == 0);
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return BI->getNumArgs() != 0;
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}
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if (auto CBI = dyn_cast<CondBranchInst>(T)) {
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assert(edgeIdx <= 1);
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return edgeIdx == CondBranchInst::TrueIdx ? !CBI->getTrueArgs().empty()
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: !CBI->getFalseArgs().empty();
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}
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// No other terminator have branch arguments.
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return false;
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}
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void swift::changeBranchTarget(TermInst *T, unsigned edgeIdx,
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SILBasicBlock *newDest, bool preserveArgs) {
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// In many cases, we can just rewrite the successor in place.
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if (preserveArgs || !hasBranchArguments(T, edgeIdx)) {
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T->getSuccessors()[edgeIdx] = newDest;
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return;
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}
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// Otherwise, we have to build a new branch instruction.
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SILBuilderWithScope B(T);
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switch (T->getTermKind()) {
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// Only Branch and CondBranch may have arguments.
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case TermKind::BranchInst: {
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auto *BI = cast<BranchInst>(T);
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SmallVector<SILValue, 8> args;
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if (preserveArgs) {
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for (auto arg : BI->getArgs())
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args.push_back(arg);
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}
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B.createBranch(T->getLoc(), newDest, args);
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BI->dropAllReferences();
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BI->eraseFromParent();
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return;
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}
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case TermKind::CondBranchInst: {
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auto CBI = cast<CondBranchInst>(T);
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SILBasicBlock *trueDest = CBI->getTrueBB();
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SILBasicBlock *falseDest = CBI->getFalseBB();
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SmallVector<SILValue, 8> trueArgs;
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SmallVector<SILValue, 8> falseArgs;
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if (edgeIdx == CondBranchInst::FalseIdx) {
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falseDest = newDest;
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for (auto arg : CBI->getTrueArgs())
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trueArgs.push_back(arg);
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} else {
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trueDest = newDest;
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for (auto arg : CBI->getFalseArgs())
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falseArgs.push_back(arg);
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}
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B.createCondBranch(CBI->getLoc(), CBI->getCondition(), trueDest, trueArgs,
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falseDest, falseArgs, CBI->getTrueBBCount(),
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CBI->getFalseBBCount());
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CBI->dropAllReferences();
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CBI->eraseFromParent();
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return;
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}
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default:
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llvm_unreachable("only branch and cond_branch have branch arguments");
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}
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}
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template <class SwitchInstTy>
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static SILBasicBlock *getNthEdgeBlock(SwitchInstTy *S, unsigned edgeIdx) {
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if (S->getNumCases() == edgeIdx)
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return S->getDefaultBB();
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return S->getCase(edgeIdx).second;
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}
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static SILBasicBlock *getNthEdgeBlock(SwitchEnumTermInst S, unsigned edgeIdx) {
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if (S.getNumCases() == edgeIdx)
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return S.getDefaultBB();
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return S.getCase(edgeIdx).second;
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}
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void swift::getEdgeArgs(TermInst *T, unsigned edgeIdx, SILBasicBlock *newEdgeBB,
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llvm::SmallVectorImpl<SILValue> &args) {
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switch (T->getKind()) {
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case SILInstructionKind::BranchInst: {
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auto *B = cast<BranchInst>(T);
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for (auto V : B->getArgs())
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args.push_back(V);
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return;
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}
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case SILInstructionKind::CondBranchInst: {
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auto CBI = cast<CondBranchInst>(T);
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assert(edgeIdx < 2);
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auto OpdArgs = edgeIdx ? CBI->getFalseArgs() : CBI->getTrueArgs();
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for (auto V : OpdArgs)
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args.push_back(V);
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return;
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}
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case SILInstructionKind::AwaitAsyncContinuationInst: {
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auto AACI = cast<AwaitAsyncContinuationInst>(T);
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switch (edgeIdx) {
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case 0:
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// resume BB. this takes the resume value argument if the operand is
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// GetAsyncContinuation, or no argument if the operand is
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// GetAsyncContinuationAddr
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if (auto contOperand = dyn_cast<GetAsyncContinuationInst>(AACI->getOperand())) {
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args.push_back(newEdgeBB->createPhiArgument(
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contOperand->getLoweredResumeType(), OwnershipKind::Owned));
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}
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return;
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case 1: {
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assert(AACI->getErrorBB());
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auto &C = AACI->getFunction()->getASTContext();
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auto errorTy = C.getErrorDecl()->getDeclaredType();
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auto errorSILTy = SILType::getPrimitiveObjectType(errorTy->getCanonicalType());
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// error BB. this takes the error value argument
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args.push_back(
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newEdgeBB->createPhiArgument(errorSILTy, OwnershipKind::Owned));
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return;
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}
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default:
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llvm_unreachable("only has at most two edges");
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}
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}
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case SILInstructionKind::SwitchValueInst: {
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auto SEI = cast<SwitchValueInst>(T);
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auto *succBB = getNthEdgeBlock(SEI, edgeIdx);
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assert(succBB->getNumArguments() == 0 && "Can't take an argument");
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(void)succBB;
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return;
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}
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// A switch_enum can implicitly pass the enum payload. We need to look at the
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// destination block to figure this out.
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case SILInstructionKind::SwitchEnumInst:
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case SILInstructionKind::SwitchEnumAddrInst: {
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SwitchEnumTermInst branch(T);
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auto *succBB = getNthEdgeBlock(branch, edgeIdx);
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assert(succBB->getNumArguments() < 2 && "Can take at most one argument");
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if (!succBB->getNumArguments())
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return;
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args.push_back(newEdgeBB->createPhiArgument(
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succBB->getArgument(0)->getType(), OwnershipKind::Owned));
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return;
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}
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// A dynamic_method_br passes the function to the first basic block.
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case SILInstructionKind::DynamicMethodBranchInst: {
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auto DMBI = cast<DynamicMethodBranchInst>(T);
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auto *succBB =
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(edgeIdx == 0) ? DMBI->getHasMethodBB() : DMBI->getNoMethodBB();
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if (!succBB->getNumArguments())
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return;
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args.push_back(newEdgeBB->createPhiArgument(
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succBB->getArgument(0)->getType(), OwnershipKind::Owned));
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return;
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}
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/// A checked_cast_br passes the result of the cast to the first basic block.
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case SILInstructionKind::CheckedCastBranchInst: {
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auto CBI = cast<CheckedCastBranchInst>(T);
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auto succBB = edgeIdx == 0 ? CBI->getSuccessBB() : CBI->getFailureBB();
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if (!succBB->getNumArguments())
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return;
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args.push_back(newEdgeBB->createPhiArgument(
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succBB->getArgument(0)->getType(), OwnershipKind::Owned));
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return;
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}
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case SILInstructionKind::CheckedCastAddrBranchInst: {
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auto CBI = cast<CheckedCastAddrBranchInst>(T);
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auto succBB = edgeIdx == 0 ? CBI->getSuccessBB() : CBI->getFailureBB();
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if (!succBB->getNumArguments())
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return;
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args.push_back(newEdgeBB->createPhiArgument(
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succBB->getArgument(0)->getType(), OwnershipKind::Owned));
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return;
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}
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case SILInstructionKind::CheckedCastValueBranchInst: {
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auto CBI = cast<CheckedCastValueBranchInst>(T);
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auto succBB = edgeIdx == 0 ? CBI->getSuccessBB() : CBI->getFailureBB();
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if (!succBB->getNumArguments())
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return;
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args.push_back(newEdgeBB->createPhiArgument(
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succBB->getArgument(0)->getType(), OwnershipKind::Owned));
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return;
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}
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case SILInstructionKind::TryApplyInst: {
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auto *TAI = cast<TryApplyInst>(T);
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auto *succBB = edgeIdx == 0 ? TAI->getNormalBB() : TAI->getErrorBB();
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if (!succBB->getNumArguments())
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return;
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args.push_back(newEdgeBB->createPhiArgument(
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succBB->getArgument(0)->getType(), OwnershipKind::Owned));
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return;
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}
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case SILInstructionKind::YieldInst:
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// The edges from 'yield' never have branch arguments.
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return;
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case SILInstructionKind::ReturnInst:
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case SILInstructionKind::ThrowInst:
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case SILInstructionKind::UnwindInst:
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case SILInstructionKind::UnreachableInst:
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llvm_unreachable("terminator never has successors");
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#define TERMINATOR(ID, ...)
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#define INST(ID, BASE) case SILInstructionKind::ID:
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#include "swift/SIL/SILNodes.def"
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llvm_unreachable("not a terminator");
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}
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llvm_unreachable("bad instruction kind");
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}
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SILBasicBlock *swift::splitEdge(TermInst *T, unsigned edgeIdx,
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DominanceInfo *DT, SILLoopInfo *LI) {
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auto *srcBB = T->getParent();
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auto *F = srcBB->getParent();
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SILBasicBlock *destBB = T->getSuccessors()[edgeIdx];
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// Create a new basic block in the edge, and insert it after the srcBB.
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auto *edgeBB = F->createBasicBlockAfter(srcBB);
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SmallVector<SILValue, 16> args;
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getEdgeArgs(T, edgeIdx, edgeBB, args);
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SILBuilderWithScope(edgeBB, T).createBranch(T->getLoc(), destBB, args);
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// Strip the arguments and rewire the branch in the source block.
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changeBranchTarget(T, edgeIdx, edgeBB, /*PreserveArgs=*/false);
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if (!DT && !LI)
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return edgeBB;
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// Update the dominator tree.
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if (DT) {
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auto *srcBBNode = DT->getNode(srcBB);
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// Unreachable code could result in a null return here.
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if (srcBBNode) {
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// The new block is dominated by the srcBB.
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auto *edgeBBNode = DT->addNewBlock(edgeBB, srcBB);
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// Are all predecessors of destBB dominated by destBB?
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auto *destBBNode = DT->getNode(destBB);
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bool oldSrcBBDominatesAllPreds = std::all_of(
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destBB->pred_begin(), destBB->pred_end(), [=](SILBasicBlock *B) {
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if (B == edgeBB)
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return true;
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auto *PredNode = DT->getNode(B);
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if (!PredNode)
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return true;
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if (DT->dominates(destBBNode, PredNode))
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return true;
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return false;
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});
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// If so, the new bb dominates destBB now.
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if (oldSrcBBDominatesAllPreds)
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DT->changeImmediateDominator(destBBNode, edgeBBNode);
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}
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}
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if (!LI)
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return edgeBB;
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// Update loop info. Both blocks must be in a loop otherwise the split block
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// is outside the loop.
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SILLoop *srcBBLoop = LI->getLoopFor(srcBB);
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if (!srcBBLoop)
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return edgeBB;
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SILLoop *DstBBLoop = LI->getLoopFor(destBB);
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if (!DstBBLoop)
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return edgeBB;
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// Same loop.
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if (DstBBLoop == srcBBLoop) {
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DstBBLoop->addBasicBlockToLoop(edgeBB, LI->getBase());
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return edgeBB;
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}
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// Edge from inner to outer loop.
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if (DstBBLoop->contains(srcBBLoop)) {
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DstBBLoop->addBasicBlockToLoop(edgeBB, LI->getBase());
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return edgeBB;
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}
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// Edge from outer to inner loop.
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if (srcBBLoop->contains(DstBBLoop)) {
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srcBBLoop->addBasicBlockToLoop(edgeBB, LI->getBase());
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return edgeBB;
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}
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// Neither loop contains the other. The destination must be the header of its
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// loop. Otherwise, we would be creating irreducible control flow.
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assert(DstBBLoop->getHeader() == destBB
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&& "Creating irreducible control flow?");
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// Add to outer loop if there is one.
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if (auto *parent = DstBBLoop->getParentLoop())
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parent->addBasicBlockToLoop(edgeBB, LI->getBase());
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return edgeBB;
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}
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/// Merge the basic block with its successor if possible.
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void swift::mergeBasicBlockWithSingleSuccessor(SILBasicBlock *BB,
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SILBasicBlock *succBB) {
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auto *BI = cast<BranchInst>(BB->getTerminator());
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assert(succBB->getSinglePredecessorBlock());
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// If there are any BB arguments in the destination, replace them with the
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// branch operands, since they must dominate the dest block.
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for (unsigned i = 0, e = BI->getArgs().size(); i != e; ++i)
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succBB->getArgument(i)->replaceAllUsesWith(BI->getArg(i));
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BI->eraseFromParent();
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// Move the instruction from the successor block to the current block.
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BB->spliceAtEnd(succBB);
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succBB->eraseFromParent();
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}
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//===----------------------------------------------------------------------===//
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// DeadEndBlocks
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//===----------------------------------------------------------------------===//
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void DeadEndBlocks::compute() {
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assert(ReachableBlocks.empty() && "Computed twice");
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// First step: find blocks which end up in a no-return block (terminated by
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// an unreachable instruction).
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// Search for function-exiting blocks, i.e. return and throw.
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for (const SILBasicBlock &BB : *F) {
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const TermInst *TI = BB.getTerminator();
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if (TI->isFunctionExiting())
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ReachableBlocks.insert(&BB);
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}
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// Propagate the reachability up the control flow graph.
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unsigned Idx = 0;
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while (Idx < ReachableBlocks.size()) {
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const SILBasicBlock *BB = ReachableBlocks[Idx++];
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for (SILBasicBlock *Pred : BB->getPredecessorBlocks())
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ReachableBlocks.insert(Pred);
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}
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}
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