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xd009642
14870d7625
* Added tests for c++ source and header files and java files. * Added VHDL to languages and tests * Updated readme Updated to reflect VHDL being added to languages
31 lines
568 B
VHDL
31 lines
568 B
VHDL
-- 30 lines 20 code 4 comments 6 blanks
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity tb is
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Port ( clk : in STD_LOGIC; -- clock
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rst : in STD_LOGIC; -- reset
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-- removed: in STD_LOGIC_VECTOR(7 downto 0)
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);
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end tb;
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-- architecture
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architecture behavioural of tb is
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signal toggle : STD_LOGIC := '0';
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begin
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-- Toggles signal
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process(clk, rst)
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begin
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if (rst='1') then
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toggle <= '0';
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else
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toggle <= not toggle;
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end if;
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end process;
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end
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