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Merge branch 'net-macb-various-fixes'
Théo Lebrun says: ==================== net: macb: various fixes Fix a few disparate topics in MACB: [PATCH net v6 1/5] dt-bindings: net: cdns,macb: allow tsu_clk without tx_clk [PATCH net v6 2/5] net: macb: remove illusion about TBQPH/RBQPH being per-queue [PATCH net v6 3/5] net: macb: move ring size computation to functions [PATCH net v6 4/5] net: macb: single dma_alloc_coherent() for DMA descriptors [PATCH net v6 5/5] net: macb: avoid dealing with endianness in macb_set_hwaddr() Patch 3/5 is a rework that simplifies patch 4/5. It is the only non-fix. Pending series on MACB are: (1) many cleanup patches, (2) patches for EyeQ5 support and (3) XDP work. Those will be sent targeting net-next/main once this series lands there, aiming to minimise merge conflicts. Old version of(1) and (2) are visible in the V2 revision [0]. [0]: https://lore.kernel.org/lkml/20250627-macb-v2-0-ff8207d0bb77@bootlin.com/ ==================== Link: https://patch.msgid.link/20250923-macb-fixes-v6-0-772d655cdeb6@bootlin.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
@@ -85,7 +85,7 @@ properties:
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items:
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- enum: [ ether_clk, hclk, pclk ]
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- enum: [ hclk, pclk ]
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- const: tx_clk
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- enum: [ tx_clk, tsu_clk ]
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- enum: [ rx_clk, tsu_clk ]
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- const: tsu_clk
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@@ -213,10 +213,8 @@
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#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
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#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
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#define GEM_TBQPH(hw_q) (0x04C8)
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#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
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#define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
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#define GEM_RBQPH(hw_q) (0x04D4)
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#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
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#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
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#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
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@@ -1214,10 +1212,8 @@ struct macb_queue {
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unsigned int IDR;
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unsigned int IMR;
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unsigned int TBQP;
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unsigned int TBQPH;
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unsigned int RBQS;
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unsigned int RBQP;
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unsigned int RBQPH;
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/* Lock to protect tx_head and tx_tail */
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spinlock_t tx_ptr_lock;
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@@ -51,14 +51,10 @@ struct sifive_fu540_macb_mgmt {
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#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
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#define MIN_RX_RING_SIZE 64
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#define MAX_RX_RING_SIZE 8192
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#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
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* (bp)->rx_ring_size)
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#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
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#define MIN_TX_RING_SIZE 64
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#define MAX_TX_RING_SIZE 4096
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#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
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* (bp)->tx_ring_size)
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/* level of occupied TX descriptors under which we wake up TX process */
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#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
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@@ -278,9 +274,9 @@ static void macb_set_hwaddr(struct macb *bp)
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u32 bottom;
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u16 top;
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bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
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bottom = get_unaligned_le32(bp->dev->dev_addr);
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macb_or_gem_writel(bp, SA1B, bottom);
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top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
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top = get_unaligned_le16(bp->dev->dev_addr + 4);
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macb_or_gem_writel(bp, SA1T, top);
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if (gem_has_ptp(bp)) {
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@@ -495,19 +491,19 @@ static void macb_init_buffers(struct macb *bp)
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struct macb_queue *queue;
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unsigned int q;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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/* Single register for all queues' high 32 bits. */
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if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
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macb_writel(bp, RBQPH,
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upper_32_bits(bp->queues[0].rx_ring_dma));
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macb_writel(bp, TBQPH,
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upper_32_bits(bp->queues[0].tx_ring_dma));
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}
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#endif
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for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
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queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (bp->hw_dma_cap & HW_DMA_CAP_64B)
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queue_writel(queue, RBQPH,
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upper_32_bits(queue->rx_ring_dma));
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#endif
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queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (bp->hw_dma_cap & HW_DMA_CAP_64B)
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queue_writel(queue, TBQPH,
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upper_32_bits(queue->tx_ring_dma));
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#endif
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}
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}
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@@ -1166,10 +1162,6 @@ static void macb_tx_error_task(struct work_struct *work)
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/* Reinitialize the TX desc queue */
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queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (bp->hw_dma_cap & HW_DMA_CAP_64B)
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queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
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#endif
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/* Make TX ring reflect state of hardware */
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queue->tx_head = 0;
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queue->tx_tail = 0;
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@@ -2474,35 +2466,42 @@ static void macb_free_rx_buffers(struct macb *bp)
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}
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}
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static unsigned int macb_tx_ring_size_per_queue(struct macb *bp)
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{
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return macb_dma_desc_get_size(bp) * bp->tx_ring_size + bp->tx_bd_rd_prefetch;
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}
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static unsigned int macb_rx_ring_size_per_queue(struct macb *bp)
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{
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return macb_dma_desc_get_size(bp) * bp->rx_ring_size + bp->rx_bd_rd_prefetch;
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}
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static void macb_free_consistent(struct macb *bp)
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{
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struct device *dev = &bp->pdev->dev;
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struct macb_queue *queue;
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unsigned int q;
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int size;
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size_t size;
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if (bp->rx_ring_tieoff) {
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dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp),
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dma_free_coherent(dev, macb_dma_desc_get_size(bp),
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bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma);
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bp->rx_ring_tieoff = NULL;
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}
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bp->macbgem_ops.mog_free_rx_buffers(bp);
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size = bp->num_queues * macb_tx_ring_size_per_queue(bp);
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dma_free_coherent(dev, size, bp->queues[0].tx_ring, bp->queues[0].tx_ring_dma);
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size = bp->num_queues * macb_rx_ring_size_per_queue(bp);
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dma_free_coherent(dev, size, bp->queues[0].rx_ring, bp->queues[0].rx_ring_dma);
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for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
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kfree(queue->tx_skb);
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queue->tx_skb = NULL;
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if (queue->tx_ring) {
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size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
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dma_free_coherent(&bp->pdev->dev, size,
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queue->tx_ring, queue->tx_ring_dma);
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queue->tx_ring = NULL;
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}
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if (queue->rx_ring) {
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size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
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dma_free_coherent(&bp->pdev->dev, size,
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queue->rx_ring, queue->rx_ring_dma);
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queue->rx_ring = NULL;
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}
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queue->tx_ring = NULL;
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queue->rx_ring = NULL;
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}
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}
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@@ -2544,35 +2543,45 @@ static int macb_alloc_rx_buffers(struct macb *bp)
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static int macb_alloc_consistent(struct macb *bp)
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{
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struct device *dev = &bp->pdev->dev;
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dma_addr_t tx_dma, rx_dma;
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struct macb_queue *queue;
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unsigned int q;
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int size;
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void *tx, *rx;
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size_t size;
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/*
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* Upper 32-bits of Tx/Rx DMA descriptor for each queues much match!
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* We cannot enforce this guarantee, the best we can do is do a single
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* allocation and hope it will land into alloc_pages() that guarantees
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* natural alignment of physical addresses.
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*/
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size = bp->num_queues * macb_tx_ring_size_per_queue(bp);
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tx = dma_alloc_coherent(dev, size, &tx_dma, GFP_KERNEL);
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if (!tx || upper_32_bits(tx_dma) != upper_32_bits(tx_dma + size - 1))
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goto out_err;
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netdev_dbg(bp->dev, "Allocated %zu bytes for %u TX rings at %08lx (mapped %p)\n",
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size, bp->num_queues, (unsigned long)tx_dma, tx);
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size = bp->num_queues * macb_rx_ring_size_per_queue(bp);
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rx = dma_alloc_coherent(dev, size, &rx_dma, GFP_KERNEL);
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if (!rx || upper_32_bits(rx_dma) != upper_32_bits(rx_dma + size - 1))
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goto out_err;
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netdev_dbg(bp->dev, "Allocated %zu bytes for %u RX rings at %08lx (mapped %p)\n",
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size, bp->num_queues, (unsigned long)rx_dma, rx);
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for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
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size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
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queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
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&queue->tx_ring_dma,
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GFP_KERNEL);
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if (!queue->tx_ring)
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goto out_err;
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netdev_dbg(bp->dev,
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"Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
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q, size, (unsigned long)queue->tx_ring_dma,
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queue->tx_ring);
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queue->tx_ring = tx + macb_tx_ring_size_per_queue(bp) * q;
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queue->tx_ring_dma = tx_dma + macb_tx_ring_size_per_queue(bp) * q;
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queue->rx_ring = rx + macb_rx_ring_size_per_queue(bp) * q;
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queue->rx_ring_dma = rx_dma + macb_rx_ring_size_per_queue(bp) * q;
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size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
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queue->tx_skb = kmalloc(size, GFP_KERNEL);
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if (!queue->tx_skb)
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goto out_err;
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size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
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queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
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&queue->rx_ring_dma, GFP_KERNEL);
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if (!queue->rx_ring)
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goto out_err;
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netdev_dbg(bp->dev,
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"Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
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size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
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}
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if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
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goto out_err;
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@@ -4309,12 +4318,6 @@ static int macb_init(struct platform_device *pdev)
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queue->TBQP = GEM_TBQP(hw_q - 1);
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queue->RBQP = GEM_RBQP(hw_q - 1);
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queue->RBQS = GEM_RBQS(hw_q - 1);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
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queue->TBQPH = GEM_TBQPH(hw_q - 1);
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queue->RBQPH = GEM_RBQPH(hw_q - 1);
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}
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#endif
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} else {
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/* queue0 uses legacy registers */
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queue->ISR = MACB_ISR;
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@@ -4323,12 +4326,6 @@ static int macb_init(struct platform_device *pdev)
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queue->IMR = MACB_IMR;
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queue->TBQP = MACB_TBQP;
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queue->RBQP = MACB_RBQP;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
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queue->TBQPH = MACB_TBQPH;
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queue->RBQPH = MACB_RBQPH;
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}
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#endif
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}
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/* get irq: here we use the linux queue index, not the hardware
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@@ -5452,6 +5449,11 @@ static int __maybe_unused macb_suspend(struct device *dev)
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*/
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tmp = macb_readl(bp, NCR);
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macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE)));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE))
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macb_writel(bp, RBQPH,
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upper_32_bits(bp->rx_ring_tieoff_dma));
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#endif
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for (q = 0, queue = bp->queues; q < bp->num_queues;
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++q, ++queue) {
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/* Disable RX queues */
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@@ -5461,10 +5463,6 @@ static int __maybe_unused macb_suspend(struct device *dev)
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/* Tie off RX queues */
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queue_writel(queue, RBQP,
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lower_32_bits(bp->rx_ring_tieoff_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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queue_writel(queue, RBQPH,
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upper_32_bits(bp->rx_ring_tieoff_dma));
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#endif
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}
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/* Disable all interrupts */
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queue_writel(queue, IDR, -1);
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