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drm/amd/display: Enable DEGAMMA and reject COLOR_PIPELINE+DEGAMMA_LUT
[WHAT]
Create DEGAMMA properties even if color pipeline is enabled, and enforce
the mutual exclusion in atomic check by rejecting any commit that
attempts to enable both COLOR_PIPELINE on the plane and DEGAMMA_LUT on
the CRTC simultaneously.
Fixes: 18a4127e93 ("drm/amd/display: Disable CRTC degamma when color pipeline is enabled")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4963
Reviewed-by: Melissa Wen <mwen@igalia.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
@@ -765,15 +765,15 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
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dm->adev->mode_info.crtcs[crtc_index] = acrtc;
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/* Don't enable DRM CRTC degamma property for
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* 1. Degamma is replaced by color pipeline.
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* 2. DCE since it doesn't support programmable degamma anywhere.
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* 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
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* 1. DCE since it doesn't support programmable degamma anywhere.
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* 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
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* Note: DEGAMMA properties are created even if the primary plane has the
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* COLOR_PIPELINE property. User space can use either the DEGAMMA properties
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* or the COLOR_PIPELINE property. An atomic commit which attempts to enable
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* both is rejected.
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*/
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if (plane->color_pipeline_property)
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has_degamma = false;
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else
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has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
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dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
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has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
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dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
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drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
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true, MAX_COLOR_LUT_ENTRIES);
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@@ -1257,6 +1257,14 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,
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if (ret)
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return ret;
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/* Reject commits that attempt to use both COLOR_PIPELINE and CRTC DEGAMMA_LUT */
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if (new_plane_state->color_pipeline && new_crtc_state->degamma_lut) {
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drm_dbg_atomic(plane->dev,
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"[PLANE:%d:%s] COLOR_PIPELINE and CRTC DEGAMMA_LUT cannot be enabled simultaneously\n",
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plane->base.id, plane->name);
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return -EINVAL;
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}
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ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info);
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if (ret)
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return ret;
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