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wifi: mt76: fix queue reg access when building WED and NPU together

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Move the offload specific parts of Q_READ/Q_WRITE into
mt76_dma_handle_read/write, which return false to fall back to
readl/writel. The WED and NPU #ifdefs now live inside those helpers
instead of selecting between mutually exclusive macro definitions, so a
kernel with both enabled supports both at runtime.

Also fixes the NPU path dereferencing a hardcoded q instead of the macro
argument.

Link: https://patch.msgid.link/20260724124813.3961474-20-nbd@nbd.name
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Felix Fietkau
2026-08-01 14:49:42 +00:00
parent 6f8d8c4580
commit 1fdf2b5958
1 changed files with 57 additions and 53 deletions
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drivers/net/wireless/mediatek/mt76/dma.h
+57 -53
View File
@@ -5,6 +5,8 @@
#ifndef __MT76_DMA_H
#define __MT76_DMA_H
#include <linux/regmap.h>
#define DMA_DUMMY_DATA ((void *)~0)
#define MT_RING_SIZE 0x10
@@ -46,73 +48,75 @@
#define MT_FCE_INFO_LEN 4
#define MT_RX_RXWI_LEN 32
static inline bool
mt76_dma_handle_read(struct mt76_queue *q, u32 offset, u32 *val)
{
#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
if (q->flags & MT_QFLAG_WED) {
*val = mtk_wed_device_reg_read(q->wed, q->wed_regs + offset);
return true;
}
#endif
#if IS_ENABLED(CONFIG_MT76_NPU)
if (q->flags & MT_QFLAG_NPU) {
struct airoha_npu *npu;
*val = 0;
rcu_read_lock();
npu = rcu_dereference(q->dev->mmio.npu);
if (npu)
regmap_read(npu->regmap, q->wed_regs + offset, val);
rcu_read_unlock();
return true;
}
#endif
return false;
}
static inline bool
mt76_dma_handle_write(struct mt76_queue *q, u32 offset, u32 val)
{
#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
if (q->flags & MT_QFLAG_WED) {
mtk_wed_device_reg_write(q->wed, q->wed_regs + offset, val);
return true;
}
#endif
#if IS_ENABLED(CONFIG_MT76_NPU)
if (q->flags & MT_QFLAG_NPU) {
struct airoha_npu *npu;
rcu_read_lock();
npu = rcu_dereference(q->dev->mmio.npu);
if (npu)
regmap_write(npu->regmap, q->wed_regs + offset, val);
rcu_read_unlock();
return true;
}
#endif
return false;
}
#define Q_READ(_q, _field) ({ \
u32 _offset = offsetof(struct mt76_queue_regs, _field); \
u32 _val; \
if ((_q)->flags & MT_QFLAG_WED) \
_val = mtk_wed_device_reg_read((_q)->wed, \
((_q)->wed_regs + \
_offset)); \
else \
if (!mt76_dma_handle_read(_q, _offset, &_val)) \
_val = readl(&(_q)->regs->_field); \
_val; \
})
#define Q_WRITE(_q, _field, _val) do { \
u32 _offset = offsetof(struct mt76_queue_regs, _field); \
if ((_q)->flags & MT_QFLAG_WED) \
mtk_wed_device_reg_write((_q)->wed, \
((_q)->wed_regs + _offset), \
_val); \
else \
if (!mt76_dma_handle_write(_q, _offset, _val)) \
writel(_val, &(_q)->regs->_field); \
} while (0)
#elif IS_ENABLED(CONFIG_MT76_NPU)
#define Q_READ(_q, _field) ({ \
u32 _offset = offsetof(struct mt76_queue_regs, _field); \
u32 _val = 0; \
if ((_q)->flags & MT_QFLAG_NPU) { \
struct airoha_npu *npu; \
\
rcu_read_lock(); \
npu = rcu_dereference(q->dev->mmio.npu); \
if (npu) \
regmap_read(npu->regmap, \
((_q)->wed_regs + _offset), &_val); \
rcu_read_unlock(); \
} else { \
_val = readl(&(_q)->regs->_field); \
} \
_val; \
})
#define Q_WRITE(_q, _field, _val) do { \
u32 _offset = offsetof(struct mt76_queue_regs, _field); \
if ((_q)->flags & MT_QFLAG_NPU) { \
struct airoha_npu *npu; \
\
rcu_read_lock(); \
npu = rcu_dereference(q->dev->mmio.npu); \
if (npu) \
regmap_write(npu->regmap, \
((_q)->wed_regs + _offset), _val); \
rcu_read_unlock(); \
} else { \
writel(_val, &(_q)->regs->_field); \
} \
} while (0)
#else
#define Q_READ(_q, _field) readl(&(_q)->regs->_field)
#define Q_WRITE(_q, _field, _val) writel(_val, &(_q)->regs->_field)
#endif
struct mt76_desc {
__le32 buf0;
__le32 ctrl;