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drm/amd/pm/ci: Use highest MCLK on CI when MCLK DPM is disabled

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[ Upstream commit 894f0d34d6 ]

When MCLK DPM is disabled for any reason, populate the MCLK
table with the highest MCLK DPM level, so that the ASIC can
use the highest possible memory clock to get good performance
even when MCLK DPM is disabled.

Fixes: 9f4b35411c ("drm/amd/powerplay: add CI asics support to smumgr (v3)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Timur Kristóf
2026-05-23 13:03:12 +02:00
committed by Greg Kroah-Hartman
parent 9a7f12105f
commit 33da7d5b6a
1 changed files with 8 additions and 0 deletions
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drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+8
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@@ -1322,6 +1322,14 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
return result;
}
if (data->mclk_dpm_key_disabled && dpm_table->mclk_table.count) {
/* Populate the table with the highest MCLK level when MCLK DPM is disabled */
for (i = 0; i < dpm_table->mclk_table.count - 1; i++) {
levels[i] = levels[dpm_table->mclk_table.count - 1];
levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
}
}
smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
dev_id = adev->pdev->device;