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dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets

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[ Upstream commit fc6e29d428 ]

The MDSS resets have so far been left undescribed. Fix that.

Fixes: 75616da712 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stable-dep-of: b0bc6011c5 ("clk: qcom: dispcc-sc7180: Add missing MDSS resets")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Konrad Dybcio
2026-01-20 12:19:25 +01:00
committed by Greg Kroah-Hartman
parent 166db4ebae
commit 5db0537dde
1 changed files with 6 additions and 1 deletions
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include/dt-bindings/clock/qcom,dispcc-sc7180.h
+6 -1
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@@ -6,6 +6,7 @@
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
/* Clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_PLL0_OUT_EVEN 1
#define DISP_CC_MDSS_AHB_CLK 2
@@ -40,7 +41,11 @@
#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
#define DISP_CC_XO_CLK 32
/* DISP_CC GDSCR */
/* Resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_RSCC_BCR 1
/* GDSCs */
#define MDSS_GDSC 0
#endif