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Revert "MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT"

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commit 078b831638 upstream.

This reverts commit 426fa8e4fe.

The commit has caused two issues on Loongson 3A4000:

1. The timestamp in dmesg become erratic, like:

    [3.736957] amdgpu 0000:04:00.0: ... ...
    [3.748895] [drm] Initialized amdgpu ... ...
    [18446744073.381141] amdgpu 0000:04:00:0: ... ...
    [1.613326] igb 0000:03:00.0 enp3s0: ... ...

2. More seriously, some workloads (for example, the test
   stdlib/test-cxa_atexit2 in the Glibc test suite) triggers an RCU
   stall and hang the system with a high probably (4 hangs out of 5
   tests).

Revert this commit to use jiffie on Loongson MIPS systems and fix these
issues for now.  The root cause may need more investigation.

Cc: stable@vger.kernel.org # 6.11+
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Xi Ruoyao
2024-12-23 17:20:41 +08:00
committed by Greg Kroah-Hartman
parent 6d76a2a72c
commit 8a844ea6d7
1 changed files with 0 additions and 1 deletions
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arch/mips/Kconfig
-1
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@@ -1084,7 +1084,6 @@ config CSRC_IOASIC
config CSRC_R4K
select CLOCKSOURCE_WATCHDOG if CPU_FREQ
select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
bool
config CSRC_SB1250